According to wikichip, TSMC's paper at a technology conference in the United States warned that logic chips are still expanding along the historical trend line, while SRAM expansion seems to have completely collapsed. What this means for future CPUs, GPUs and SoCs is that they may become more expensive due to the slow scaling of the SRAM cell area.
In August this year, according to foreign media reports, the yield rate of TSMC’s N3E process exceeded expectations, and the yield rate of N3ESRAM was significantly higher than that of N3. Due to a leak of TSMC's internal data, the data shows that the N3E process is developing very smoothly, and the yield rate is outstanding, and it can be put into production about six months in advance.
Wikichip pointed out that TSMC talked about the 3nm basic version (N3B) node and some data of the 3nm enhanced version (N3E). But this made people discover that compared with N5, TSMC did not state in August that the HD SRAM density of the new technology has almost no change. More expensive.
Focusing on the future, the demand for cache SRAM in all walks of life will only increase, and this will make it difficult to reduce the chip area occupied by SRAM for a while, and it will not be possible to achieve obvious cost benefits with the N5 node. Modern CPUs, GPUs, and SoCs all use large amounts of SRAM for various caches when processing large amounts of data, because fetching data directly from memory is extremely inefficient, especially for various artificial intelligence (AI) and machine learning (ML) workloads In terms of.
Consider disaggregating into separate chips on cheaper nodes, like AMD does with its 3D V-Cache processors. Or use alternative memory technologies like eDRAM or FeRAM as cache.
In any case, slowing SRAM scaling using FinFET-based nodes at 3nm and above seems to be the main challenge for chip designers in the next few years, and the possible impact for you is the price increase of end products, such as Apple with the A17 chip iPhone 15 Pro series.