TSMC's Advanced 3D Packaging: Competitive Edge for Distributors in Small Chip Era

Despite the global semiconductor industry experiencing a period of adjustment, various advanced semiconductor technologies continue to advance. TSMC's advanced packaging platform, 3D Fabric, introduces derivative technologies of its 3D wafer stacking technology called "SoIC" that offer cost competitiveness. Industry experts in electronic components distribution note that SoIC-P, which utilizes the micro-bump process, is TSMC's counterpart to Intel's Foveros 3D packaging technology. In terms of launch timelines, TSMC has taken the lead in mass production of high-threshold 3D chip technology with its original bumpless version, the more efficient "SoIC-X."

According to supply chain professionals in the packaging and testing industry, the initial version of SoIC-X still provides the best results in terms of tighter pitch spacing and performance enhancement, enabling 3D chiplets to approach the existing System-on-Chip (SoC) concept and serving as one of the solutions to the physical limitations faced by 2D scaling.

SoIC-X represents TSMC's most advanced 3D packaging technology in the global competition among leading semiconductor manufacturers. While Intel announced Foveros several years ago, its use of micro-bump technology puts it slightly behind in TSMC's perspective, considering it as a slightly older generation technology.

As the technology gradually matures, TSMC has reintroduced the micro-bump process after exploring the bumpless approach, providing a relatively competitive cost advantage without competing with chip customers.

Industry insiders affirm that the future will be characterized by "chiplet competition." For instance, Intel plans to launch new processors in 2023 and 2024 that adopt the "Tile" architecture, incorporating the concept of smaller chiplets. These processors utilize the most advanced processes for the CPU while leveraging mature processes for I/O chips, achieving cost savings and maintaining performance.

Intel has also revealed the future direction of Foveros, including Foveros Omni and Foveros Direct, with the latter introducing copper-to-copper direct bonding for 3D wafer stacking. This development aligns it with TSMC's SoIC-X technology.

In the CPU chip market, AMD emerges as a prominent adopter of TSMC's 3D SoIC technology. Besides utilizing "SoIC+CoWoS" 3D packaging for high-performance AI chips in supercomputers, AMD has also released multiple generations of the gaming CPU series called "X3D."

"Thermal management" has become a critical issue in the era of 3D chips. Recently, reports of overheating in AMD's X3D gaming CPUs have surfaced. Industry experts acknowledge that semiconductor manufacturers have already conducted evaluations regarding materials, cooling, and packaging in the semiconductor process. They have achieved a certain level of yield. However, how end-users utilize the chips and how chip manufacturers fine-tune them are factors beyond the control of the production side.

Of course, compared to TSMC's major customers such as NVIDIA, Apple, Qualcomm, and others, AMD has shown a relatively proactive approach. AMD is just beginning to embrace the era of smaller chiplets. By potentially sacrificing a small degree of performance, AMD can contribute to the overall learning and accumulation of experience in the 3D chip supply chain, allowing this new technology to mature gradually.