Intel Introduces PowerVia Technology for Enhanced Chip Performance

Intel, a leading manufacturer of electronic components, has announced that it will be showcasing its research and development achievements in PowerVia backside power delivery technology at the 2023 Very Large Scale Integration (VLSI) Technology and Circuits Symposium, taking place in Kyoto, Japan from June 11th to 16th.

PowerVia technology, expected to be implemented in conjunction with Intel's 20A manufacturing process in 2024, aims to improve the power transmission and signal wiring conditions of chips. If successfully implemented, PowerVia has the potential to give Intel a significant competitive advantage in the semiconductor manufacturing industry, surpassing its competitors by a margin of over two years, as analyzed by AnandTech.

According to reports from The Verge and The Register, Intel has highlighted the increasing demand for smaller, faster, and more powerful transistors in the field of artificial intelligence (AI) and imaging. However, the growing complexity of wiring has become a significant challenge. PowerVia, being the industry's first application of backside power delivery in chips, is expected to address this long-standing interconnect technology obstacle that has troubled the industry for decades.

The PowerVia technology separates power lines from signal lines and relocates all power lines to the backside of the silicon wafer. This approach aims to simplify chip design, eliminating the need for complex routing of power and signal lines that contribute to the "increasingly chaotic network," as described by Intel.

PowerVia offers a significant advantage by providing more space, allowing for larger power and signal lines, thus enhancing conductivity. Intel believes that PowerVia can lower the manufacturing cost of interconnect wiring and deliver higher chip performance.

The Intel 20A manufacturing process is expected to bring two major changes, namely transitioning from the previous FinFET transistor design to RibbonFET and introducing PowerVia. To avoid the nightmare of process delays, Intel has separated the development of RibbonFET and PowerVia technologies. This approach enables Intel to focus on one technology at a time, once it has successfully achieved significant milestones in the development of the other.

This "separate development" strategy is evident in the Blue Sky Creek test chip, which is used for production testing and to assist in the advancement of PowerVia technology. Blue Sky Creek combines new and mature technologies, including PowerVia, the same front-end interconnect technology as Intel 20A, FinFET transistor design from the already deployed Intel 4, Nano TSV (nanoscale through-silicon vias), and the energy-efficient Crestmont cores found in Intel's upcoming generation of Core series processors, the Meteor Lake CPU.

Intel's test results show that Blue Sky Creek achieves a performance improvement of over 6% compared to the Intel 4 reference design. Additionally, thanks to the utilization of PowerVia technology, the bare chip exhibits a battery unit utilization rate of over 90%, a significantly high level compared to previous designs.