As TSMC's largest testing and packaging facility, the AP6 factory, becomes operational, the company's production capacity for 3D packaging chips will significantly increase. TSMC's 3D packaging technology currently includes System-on-Integrated Chip (SoIC), Chip-on-Wafer-on-Substrate (CoWoS), and Integrated Fan-Out (InFO) packaging. According to the Electronic Times, the development of TSMC's SoIC packaging technology strengthens its collaboration with OSAT (Outsourced Semiconductor Assembly and Test) companies.
SoIC packaging technology enables the integration of heterogeneous and homogeneous chips on a single substrate, making it suitable for manufacturing HPC processors, consumer-grade CPUs, GPUs, and mobile processors. As this type of packaging business expands, TSMC's collaboration with major players in the substrate packaging field, such as ASE and Amkor, becomes increasingly important. This aligns with ASE's previous annual report, where the company stated that 3D packaging and testing would return to traditional OSAT manufacturers.
The increasing demand for GPU accelerators for artificial intelligence by NVIDIA has led to a surge in TSMC's CoWoS packaging requirements. Consequently, the company is focused on enhancing its CoW (Chip-on-Wafer) capabilities. However, companies like ASE and Siliconware have certain areas of expertise surpassing TSMC. Thus, collaborating with these companies will help enhance production capacity.
Supply chain insiders indicate that TSMC has outsourced certain processes of CoWoS and InFO packaging to OSAT companies, forming a mature partnership model.
It is reported that TSMC has sought assistance from ASE Group, as they excel in "oS" (on-Substrate) packaging technology. Additionally, the profit margin in the "oS" field is slightly lower compared to the CoW field. Industry insiders reveal that for high-end 2.5D packaging, TSMC is willing to collaborate with OSAT companies like Siliconware, while ASE's involvement is relatively lower.