Next-Gen PLC: Twin 2.5 Bit Units, TLC-Like Speeds

Samsung Electronics, a leading innovator in the field of advanced semiconductor technology, has announced its strategic roadmap for the production of the highly anticipated 9th generation V-NAND flash memory. Set to be realized in the coming year, this cutting-edge memory solution will continue to employ a dual-stack architecture, boasting an impressive layer count exceeding 300.

Simultaneously, SK Hynix, a prominent player in the semiconductor industry, has outlined its timeline for the commencement of mass production of an advanced NAND flash architecture. This architecture, comprised of a three-stack design and a remarkable 321 layers, is projected to become operational in the first half of 2025.

These advancements reflect the persistent drive to enhance storage density through various means beyond the augmentation of layer count alone. Notably, the commercialization of 4-bit per cell (QLC) 3D NAND flash has contributed to the accessibility of solid-state drives (SSDs), transforming them into a cost-effective solution for data storage needs.

While indications of SSD price fluctuations have emerged, several industry giants have embarked on the exploration of the next evolutionary step: the 5-bit per cell (PLC) approach. This forward-looking innovation is anticipated to unlock increased capacities and accelerated speeds for SSDs, catering to the growing demands of the digital era.

Presenting at the prestigious 2023 Flash Memory Summit (FMS), SK Hynix unveiled their pioneering research outcomes in the domain of 5-bit per cell (PLC) technology. This trailblazing technique draws parallels with the Twin BiCS FLASH technology introduced in 2019, leveraging a dual-unit paradigm for heightened efficiency in data writing.

Within the 5-bit per cell paradigm, a single storage unit accommodates a remarkable 32 distinct threshold voltages, underscoring the sophistication of modern memory solutions. Conventional PLC write and validation processes have historically posed challenges, necessitating novel strategies for efficient data handling. Responding adeptly, SK Hynix has devised a groundbreaking PLC design, seamlessly subdividing a 5-bit per cell unit into two 2.5-bit per cell subunits. The amalgamation of data from these subunits enables PLC write times to approximate those of TLC (3-bit per cell) units.

Innovation in this realm is not uncharted territory, as demonstrated by Solidigm's pioneering introduction of the first SSD leveraging PLC-NAND technology a year ago. This innovation, retaining the architectural layout of QLC-NAND, demonstrated the potential of 5-bit per cell configurations, driving density improvements to an impressive 23.3 Gbit/mm².

With the advent of the forthcoming 9th generation 321-layer TLC-NAND, SK Hynix aims to propel storage density even further, with projections exceeding 20 Gbit/mm². However, the pursuit of increased layer counts entails intricate operational steps and elevated production costs, indicating that early iterations of these products might reflect a premium pricing tier.