Samsung to Mass Produce 3nm & 4nm Chips in 2H 2024
On November 3rd, Samsung Electronics, a prominent South Korean technology company, announced its plans to initiate chip production using its advanced second-generation 3nm (SF3) process technology and the enhanced 4nm (SF4X) process technology. This significant advancement is scheduled to commence in the latter half of 2024 and is poised to enhance Samsung's competitive position in the semiconductor foundry market while offering a compelling opportunity for new product development.
In an official statement, Samsung Electronics pointed to the anticipated resurgence in the overall market driven by the recovery in the mobile industry and sustained growth in the high-performance computing (HPC) sector. In response to this positive market trend, the company has outlined its strategic vision to begin mass production of its second-generation 3nm process and the fourth-generation 4nm process, tailored specifically for high-performance computing applications, during the latter half of 2024. This forward-thinking move is designed to strengthen Samsung's technological competitiveness.
According to available data, Samsung's second-generation 3nm (SF3) process technology represents a significant leap forward from the initial 3nm (SF3E) process technology, which had primarily been utilized for small-scale chip production, particularly in cryptocurrency mining applications. Samsung underscores that this second-generation 3nm technology offers increased design versatility by enabling the use of varying Gate-All-Around (GAA) transistor/nanoribbon channel widths within the same unit type.
While Samsung refrained from making a direct comparison between the two generations of 3nm processes, they have emphasized that the second-generation 3nm technology presents more substantial improvements than the second-generation 4nm process technology (4LPP). These enhancements encompass a 22% performance boost at equivalent power and complexity levels, or a notable 34% reduction in power consumption at identical frequencies and transistor counts. Moreover, it is expected to result in a 21% reduction in chip area. The second-generation 3nm process technology is set to enter mass production in the latter half of 2024, promising greater design flexibility compared to its predecessor.
Furthermore, Samsung is actively advancing its 4nm process technology. The company is preparing to introduce an enhanced iteration of the 4nm (SF4X) process technology, thoughtfully designed for high-performance CPUs and GPUs tailored to the demanding requirements of data center applications. This marks a significant milestone as the first process node expressly engineered for high-performance computing (HPC) applications in recent years.
The enhanced 4nm process technology by Samsung is anticipated to deliver a 10% performance increase while concurrently reducing power consumption by 23%. Although specific benchmark details were not disclosed by Samsung, it is reasonable to assume that the comparison is relative to their existing standard 4nm process technology. The development of this improved process was achieved through innovative transistor redesign in the source-drain regions, meticulous performance evaluation under high-stress conditions, the implementation of advanced transistor-level design technology co-optimization (T-DTCO), and thorough execution.
Reports emphasize Samsung's commitment to realizing a minimum operating voltage (Vmin) of 60mV for CPU silicon validation with the enhanced 4nm process technology, reducing the variation in standby current (IDDQ) by 10%, ensuring stable operation at voltages exceeding 1V without compromising performance, and elevating the process quality of SRAM through a meticulously refined MOL architecture.
