Samsung Set to Launch Advanced 3D Chip Packaging Tech SAINT in 2024

Samsung is actively preparing to compete with TSMC's CoWoS packaging technology by developing its own advanced packaging solutions. The company is slated to unveil its state-of-the-art 3D chip packaging technology, known as SAINT (Samsung Advanced Interconnection Technology), in 2024. SAINT aims to integrate the memory and processors of high-performance chips, including AI chips, within more compact packages.

Samsung's SAINT encompasses three distinct packaging technologies:

l SAINT S - designed for the vertical stacking of SRAM memory chips and CPUs

l SAINT D - tailored for the vertical packaging of core IPs such as CPUs, GPUs, and DRAM

l SAINT L - engineered for the stacking of application processors (AP)

Following successful validation tests, Samsung plans to expand its services in the latter part of the coming year after further testing with customers. The objective is to enhance the performance of AI chips in data centers and application processors featuring embedded AI functionality in mobile phones.

Should the current trajectory persist, Samsung's SAINT holds promise in capturing a segment of the market share from its competitors. However, the satisfaction of technology giants such as NVIDIA and AMD with the offering remains to be determined.

Reports indicate that Samsung is actively vying for a substantial number of HBM memory orders, critical for supporting NVIDIA's next-generation Blackwell AI GPU. Samsung's latest Shinebolt "HBM3e" memory has also secured orders for AMD's next-generation Instinct accelerator. Nonetheless, in comparison to NVIDIA's commanding presence in the AI market, Samsung's order proportion is comparatively lower. Foreseen orders for HBM3 from both companies are anticipated to be reserved and fulfilled before the conclusion of 2025, with the current market demand for AI GPUs exhibiting continued strength.

As companies transition from conventional single-chip designs to innovative Chiplet-based architectures, the focus on advanced packaging becomes increasingly prominent. TSMC, in response, is expanding its CoWoS facilities and making significant investments in testing and upgrading its 3D stacking technology, SoIC, to meet the evolving demands of prominent customers like Apple and NVIDIA. In July of the current year, TSMC announced a substantial investment of 90 billion New Taiwan Dollars (approximately 2.9 billion USD) to establish a cutting-edge advanced packaging plant. Concurrently, Intel has commenced leveraging its latest generation 3D chip packaging technology, Fooveros, for the production of advanced chips.