AMD's New FPGA: 16nm Upgrade, 30% Lower Power

On March 5th, AMD officially launched its cutting-edge FPGA product, the "Spartan UltraScale+," representing the sixth generation within the esteemed Spartan FGPA series. Positioned as the latest addition to AMD's portfolio of cost-optimized FPGAs and adaptive SoCs, this series is purpose-built for cost-sensitive edge applications, promising superior cost-effectiveness and heightened energy efficiency for a variety of I/O-intensive edge scenarios.

The Spartan UltraScale+ series encompasses a diverse array of nine sub-models. Noteworthy variants include the SU10P, SU25P, and SU35P, designed to excel in I/O expansion capabilities, and the SU50P, SU55P, and SU65P, tailored for board management. Additionally, the SU100P, SU150P, and SU200P models cater specifically to IoT and industrial connectivity settings. These variants boast distinctions in logic units, I/O count, I/O logic ratio, on-chip memory, DDR/PCIe hardware IP, GTH transceivers, and packaging, thereby addressing the unique needs of various edge devices, sensing applications, and control systems.

With specifications reaching up to 218,000 logic units, a maximum on-chip memory of 26.79Mb (UltraRAM), support for up to 572 I/O, and compatibility with 3.3V voltage, the Spartan UltraScale+ series facilitates versatile connectivity for edge sensing and control applications. Notably, this series marks a significant milestone as AMD's inaugural FPGA product featuring a hardened LPDDR5 memory controller, achieving a maximum frequency of 4266MHz while maintaining compatibility with LPDDR4X and supporting up to eight PCIe 4.0 interfaces.

The series offers a range of packaging options, including CSP and BGA, with dimensions varying from a compact 10x10mm to a maximum of 23x23mm, including an intermediary size of 12x12mm. This reduction in footprint, in comparison to the previous Spartan 7 series, enhances support for additional GPIO.

Relative to its predecessor, the Atrix 7 series, the Spartan UltraScale+ series maintains a smaller size while supporting an equivalent number of LC user logic elements, concurrently upgrading from a soft DDR memory controller to a hardened LPDDR5 memory controller. The implementation of a validated 16nm FinFET manufacturing process results in a substantial reduction of total power consumption by up to 30% compared to the preceding 28nm process used in the Atrix 7 series. Furthermore, interface connection power consumption experiences a commendable decrease of up to 60%.

Beyond its marked improvements in energy efficiency, the series exhibits elevated performance metrics, boasting architecture performance up to 1.9 times higher than the Atrix 7 series. Additional advancements include a 1.2 times increase in I/O count, 2.4 times increase in I/O logic units, 5 times increase in memory controller bandwidth, 4 times increase in PCIe bandwidth, and 2.5 times increase in transceiver bandwidth.

Noteworthy features of the Spartan UltraScale+ series extend beyond performance enhancements to include an extension of operational uptime, fortified single-event upset performance, expedited and secure configuration processes, and heightened overall reliability. As a testament to AMD's commitment to user-friendly development, the series leverages powerful development tools, requiring only the Vivado design suite tool and the Vitis unified software platform for comprehensive FPGA and adaptive SoC product support. This streamlined approach incorporates over 100 soft cores, significantly reducing the learning curve and supporting a seamless end-to-end design verification process.

Anticipated for release in the first half of 2025, the Spartan UltraScale+ FPGA series samples and evaluation kits are poised to set new benchmarks in FPGA technology. Relevant technical documentation is readily available, and support for AMD Vivado design suite tools is slated to commence from the fourth quarter of 2024.