SK Hynix Adopts 6th Gen 1c for HBM4 Memory

At the recent IEEE International Memory Workshop, SK Hynix, a prominent player in the memory chip industry, announced significant advancements in the development of HBM4E memory technology. With a shortened development cycle of just one year, SK Hynix is leveraging cutting-edge sixth-generation 10nm-class 1c process technology to construct 32Gb DRAM bare die for HBM4E memory.

Despite competitors' lag in mass-producing sixth-generation 10nm-class 1c process DRAM chips, SK Hynix is poised to lead the market alongside Samsung, with both companies gearing up for mass production later this year. This puts them ahead of Micron, which is expected to commence production in 2025.

SK Hynix's current HBM3E technology utilizes the fifth-generation 10nm-class 1b process, and while plans for updating the DRAM bare die process for HBM4 are in progress, they remain unconfirmed.

According to reports from The Elec, SK Hynix is accelerating the mass production timeline for HBM4 to the latter half of 2025, sticking with the fifth-generation 10nm-class 1b process to maintain developmental consistency.

Mainstream HBM3E products currently employ 24Gb DRAM chips, offering a single-stack capacity of up to 24GB through eight layers of stacking. Future advancements with HBM4E, transitioning to 32Gb DRAM bare die, could potentially yield single-chip capacities of 48GB with 12-layer stacking and even 64GB with a 16-layer version, unlocking broader applications in the realm of artificial intelligence.

Kim Kwi Wook, representing SK Hynix, forecasts significant performance enhancements for HBM4E, including a 40% increase in bandwidth, a 30% boost in density, and a 30% improvement in efficiency compared to HBM4. However, concerns regarding low yield rates currently deter the adoption of hybrid bonding technology for SK Hynix's next-generation HBM4.