Samsung 2nm Chips in 2025: 17% Smaller with BSPDN

Recent reports reveal that Samsung's semiconductor foundry plans to commence production of its first-generation 2nm chips next year, leveraging an increased EUV (Extreme Ultraviolet) lithography layer count of 26—an upgrade of 30% from the current 20 layers used in its 3nm process.

ASML, the sole global provider of EUV lithography machines, plays a pivotal role in this technological leap. EUV lithography is essential for fabricating high-density circuits on silicon wafers, a critical requirement for modern processors found in smartphones and other advanced electronics.

The upgraded 26-layer EUV process will enable Samsung’s 2nm chips to accommodate more transistors, thereby supporting more complex System on Chip (SoC) functionalities while consuming less power. These new 2nm chips are anticipated to be 17% smaller, 18% more powerful, and 15% more energy-efficient compared to the previous generation.

In addition to the increased EUV layers, Samsung will implement Back-Side Power Delivery Network (BSPDN) technology in its 2nm chips. This innovation, which relocates power delivery lines to the back of the chip, results in a 17% reduction in chip size. It also minimizes voltage drop by providing additional space for larger routing lines, enhancing overall performance and efficiency. Intel's similar PowerVia technology demonstrates its effectiveness in improving chip robustness and efficiency.

Looking forward to 2027, Samsung plans to introduce its 1.4nm node, with EUV layers expected to exceed 30. This advancement will further boost transistor density, leading to even more powerful and energy-efficient processors. TSMC, a key competitor, is also advancing its technology with up to 25 EUV layers in its 3nm process and plans to begin production of 2nm chips next year, with a 1.4nm node projected for 2027-2028.

Since adopting EUV lithography in 2018, transitioning from 10nm to 7nm, Samsung has continued to lead in innovation. This includes its DRAM production, with the sixth-generation 10nm DRAM chips utilizing seven EUV layers. Competitor SK Hynix uses five EUV layers in its DRAM manufacturing.