TSMC and Intel to Showcase 2nm Technology at IEDM

At the upcoming International Electron Devices Meeting (IEDM) in San Francisco this December, Intel is making strides to reestablish its leadership in chip manufacturing, while TSMC is taking significant steps to define the future of the field.

TSMC researchers are set to unveil their N2 process technology, a cutting-edge 2nm node designed for computing in AI, mobile, and high-performance computing (HPC) applications. Meanwhile, Intel engineers will discuss the scaling of RibbonFET, their next-generation nanosheet transistor technology.

At IEDM, TSMC is expected to report that its N2 process will deliver 15% faster performance, 30% lower power consumption, and a 15% increase in chip density compared to its N3 process introduced in 2022. The N2 interconnect stack, featuring a cross-section of copper redistribution layers, highlights seamless integration with advanced 3D technologies.

TSMC's paper, authored by G. Yeap and others, will showcase the 2nm platform’s highly efficient nanosheet transistors and interconnect devices, optimized for AI, HPC, and mobile system-on-chip (SoC) applications. Additionally, they will present a record-breaking SRAM macro with a density of 38Mbits per square millimeter.

The paper will also explore mid-end (MEOL) and back-end (BEOL) interconnect features, including scalable copper-based redistribution layers for flexible I/O pad placement, reduced resistance barriers, and flat passivation layers to improve reliability. TSMC's N2 platform has met wafer-level reliability requirements and passed initial qualification tests, with full qualification expected by 2025 and mass production slated for 2026.

Intel's paper, led by A. Agrawal, will demonstrate how the company is advancing nanosheet technology (RibbonFET) using 6nm gates and 45nm contact poly pitch (CPP), without compromising electron mobility. Their research shows that when gate lengths reach 18nm, drain-induced barrier lowering (DIBL) is reduced as silicon thickness scales from 10nm to 1.5nm. Intel is expected to use its Intel 20A process (a 2nm node) for RibbonFET production but is focusing more on the transition to Intel 18A (1.8nm).

Intel researchers will also highlight that electron mobility is maintained until the nanosheet’s silicon thickness reaches 3nm, after which surface roughness introduces challenges. Their findings detail how short-channel control and work function engineering achieve low-threshold voltages at silicon thicknesses below 4nm.