Samsung Adjusts 1c DRAM Design for HBM4 Mass Production

According to reports from South Korea, Samsung Electronics is revising the design of its 6th-generation 1c-nanometer (10nm-class) DRAM to enhance yield rates and ensure the mass production of its high-bandwidth memory, HBM4.

Earlier rumors suggested that Samsung had planned to complete the development of its 1c DRAM process by the end of 2024 and enter mass production. However, due to lower-than-expected yield rates, the timeline was delayed by six months, with completion now expected in June 2025. This delay also affects the anticipated mass production of HBM4, which was initially scheduled for the second half of 2024.

Recent reports indicate that Samsung's trial production of the 1c DRAM at the end of 2024 did not meet expectations, with yields typically ranging between 60% and 70% during the ramp-up phase. To address this issue, Samsung has decided to adjust its design. While the core circuitry width remains unchanged, the requirements for the peripheral circuitry width have been relaxed. This adjustment is expected to significantly improve yield rates, ensuring stable mass production of HBM4.

Samsung aims to begin mass production of 1c-nanometer DRAM by June 2025, paving the way for HBM4 production. As a crucial element of Samsung's future memory business, securing high yields in the 1c DRAM process is vital to maintaining its competitive edge.

In contrast, rival SK Hynix is set to begin mass production of 1c-nanometer DRAM chips as early as February 2025, positioning itself as the world's first memory manufacturer to utilize 1c-nanometer technology for DRAM production.