Marvell Announces First 2nm Chip

On March 3, 2025 (local time in the U.S.), Marvell Technology, a leading provider of data infrastructure semiconductor solutions, introduced its first 2nm silicon IP designed for next-generation AI and cloud infrastructure. This advanced chip, manufactured using TSMC's 2nm process, is part of Marvell's platform for developing custom XPUs, switches, and other technologies aimed at enhancing the performance, efficiency, and cost-effectiveness of global cloud operations.

Marvell projects that custom silicon will account for approximately 25% of the accelerated computing chip market by 2028, driven by an anticipated 45% annual growth in total addressable market (TAM).

The company's platform strategy revolves around developing a comprehensive semiconductor IP portfolio, including electrical and optical SerDes, interconnects for 2D and 3D devices, advanced packaging technologies, silicon photonics, custom high-bandwidth memory (HBM) architectures, on-chip static random-access memory (SRAM), system-on-chip (SoC) architectures, and compute interfaces such as PCIe Gen 7. These fundamental building blocks enable the development of AI accelerators, CPUs, optical DSPs, high-performance switches, and other critical technologies.

Since launching its industry-leading 5nm data infrastructure silicon platform in 2020, Marvell has remained at the forefront of advancing semiconductor technology. The company introduced its 3nm platform in 2022 and produced its first chip in 2023, with multiple industry-standard and custom silicon products now in development and production.

Sandeep Bharathi, Chief Development Officer at Marvell, stated:
"Our platform approach accelerates the development of market-leading high-speed SerDes and other critical technologies on the latest process nodes. This allows Marvell and its partners to advance the next generation of XPUs and AI acceleration infrastructure. Our longstanding collaboration with TSMC has been instrumental in developing complex chip solutions with industry-leading performance, transistor density, and efficiency."

Additionally, Marvell introduced 3D synchronous bidirectional I/O, operating at speeds of up to 6.4 Gbits/s, to enhance vertical chip stacking connectivity. Traditionally, I/O pathways in chip stacks have been unidirectional. The transition to bidirectional I/O enables up to 2× bandwidth improvement or a 50% reduction in connection points, providing greater design flexibility.

As semiconductor designs become increasingly complex, advanced chip architectures surpass the limitations of conventional photomask technology used in silicon patterning. It is estimated that 30% of high-end node processors will adopt chiplet-based designs, integrating multiple dies into a single package. With 3D synchronous bidirectional I/O, engineers can create highly integrated 2.5D, 3D, and 3.5D device stacks that deliver enhanced functionality while maintaining monolithic-like performance.

“TSMC is pleased to collaborate with Marvell in pioneering a platform for advancing accelerated infrastructure on our 2nm process technology,” said Kevin Zhang, senior vice president of business development at TSMC. “We are looking forward to our continued collaboration with Marvell in the development of leading-edge connectivity and compute products utilizing TSMC's best-in-class process and packaging technologies.”