TSMC Reportedly Secures 2nm Orders from Intel

According to Taiwanese media outlet Economic Daily Japan, Intel has officially placed orders for TSMC's latest 2nm process technology, following in the footsteps of AMD. This move marks a significant milestone for TSMC's advanced node adoption across major industry players.

Intel has long been one of TSMC's key partners for advanced manufacturing processes. In February last year, Intel CEO Pat Gelsinger confirmed that the company had entrusted TSMC with the production of two critical compute tiles for upcoming processors. These tiles were later integrated into the Intel Core Ultra 200V laptop series (codenamed Lunar Lake) and Intel's first AI desktop processor series, Core Ultra 200S (codenamed Arrow Lake). These chips utilize various TSMC nodes, including N3B for compute tiles, N5P for GPU tiles, and N6 for SoC and I/O tiles.

Recent developments suggest that Intel and TSMC have already initiated collaboration on a 2nm-based processor component, likely to be a compute tile for Intel's upcoming Nova Lake PC processors, expected to debut next year.

TSMC's latest shareholder report confirms that its 2nm process technology development is progressing as planned. The platform features the first-generation nanosheet transistor architecture, delivering notable improvements in performance and power efficiency. The company also disclosed that major clients have completed the design of 2nm silicon IP and have started the verification process. In addition, TSMC is advancing the development of low-resistance contacts and ultra-high-performance metal-insulator-metal (MIM) capacitors to further enhance the capabilities of its 2nm node.

TSMC emphasized that its 2nm platform is leading the industry in supporting the growing demand for energy-efficient, high-performance computing. Nearly all major IC innovators are currently working closely with the company on next-generation designs.

Notably, AMD recently announced on April 15 that its next-generation AMD EPYC processor, codenamed Venice, has become the world's first high-performance computing (HPC) product to complete tape-out using TSMC's 2nm (N2) process. This marks the first time AMD has been the lead partner for TSMC's newest node—a position historically held by Apple.