Semiconductor Giants Battle for Panel-Level Packaging Leadership

Fan-out panel-level packaging (FOPLP) is rapidly gaining recognition as the next-generation advanced packaging technology. Industry leaders including TSMC, ASE Technology Holding, and Powertech Technology are actively advancing their capabilities to seize opportunities presented by high-integration packaging demands from major high-performance computing chipmakers such as Nvidia and AMD.

These top semiconductor companies are intensifying their focus on fan-out panel-level packaging, each strategically positioning to drive a new wave of competitive market activity.

According to industry sources, TSMC's technology, known as CoPoS (Chip-on-Panel-on-Substrate), will establish production capacity in Chiayi with a pilot line expected by 2026. ASE has already launched a 300x300mm fan-out panel-level packaging production line in Kaohsiung. Powertech, with the longest experience in this area, achieved volume production as early as 2019 under its PiFO (Pillar Integration Fan-Out) technology.

Experts highlight that fan-out panel-level packaging offers significant advantages for high-performance computing. Compared to wafer-based processes, panel substrates provide larger areas and support heterogeneous integration, allowing incorporation of circuits with 5G communication filter functions. This integration significantly enhances post-packaging chip performance and functionality, making it highly suitable for applications in 5G communications, Internet of Things (IoT) devices, and other consumer electronics—facilitating further miniaturization of products.

TSMC's CoPoS technology primarily targets AI and high-performance computing (HPC) applications, with volume production anticipated by 2028. This process evolves from the CoWoS technology, transitioning to a panel-based square design that supports larger chip output. Recently, TSMC revealed at a North American technology forum its latest A14 process and announced plans to begin mass production in 2027 of a new CoWoS technology featuring a 9.5x larger photomask size, enabling more logic and memory chips to be integrated into a single package—trends that align closely with CoPoS development.

ASE's 300x300mm fan-out panel-level packaging production line employs the Fan-Out process, already in volume production. Powertech's PiFO technology is reported to share technical similarities with TSMC's CoPoS.