TSMC Accelerates U.S. Advanced Packaging Plant Build in 2028

According to industry sources, TSMC is set to begin construction on two state-of-the-art advanced packaging plants in the United States by 2028. These facilities are designed to expand support for cutting-edge System on Integrated Chips (SoIC) and Chip-on-Passive-Substrate (CoPoS) technologies, aiming to meet the growing local demand for AI and high-performance computing (HPC) chip packaging.

The new packaging facilities will be integrated with TSMC's third U.S. wafer fab (Fab 21 Phase 3), which will adopt 2nm (N2) and A16 process nodes. TSMC has reportedly notified equipment partners to begin moving in tools during the second quarter of 2025.

Unlike initial expectations for CoWoS (Chip-on-Wafer-on-Substrate), TSMC plans to introduce SoIC and CoPoS technologies first. Among the advanced packaging technologies currently in production, SoIC is considered TSMC's most advanced and will be used in tandem with later-stage technologies like CoWoS and the emerging CoPoS.

While CoPoS is still in its early development stage, SoIC has reached a higher level of maturity and is already used in mass production. In addition to AMD, major technology firms such as Apple, NVIDIA, and Broadcom are expected to integrate SoIC into their high-end product lines. TSMC plans to establish its first CoPoS pilot line in 2026, with mass production scheduled for its Chiayi AP7 facility between late 2028 and 2029.

TSMC has also announced that both its third and fourth U.S. wafer fabs will utilize N2 and A16 nodes, while its fifth and sixth fabs will implement even more advanced process technologies.