IBM & Lam Research Advance Sub-1nm Chip Tech

On March 10, 2026, IBM and Lam Research announced a five-year collaboration to push logic chip scaling below 1nm using High NA EUV lithography and Lam Research's Aether dry photoresist technology. The joint development will take place at IBM's research campus in Albany, New York.

The two companies, partners for over a decade, have a track record of advancing 7nm process development, nanosheet transistor architectures, and early EUV process integration. IBM's global first 2nm node chip, released in 2021, marked a milestone in their ongoing collaboration. Under the new agreement, the focus shifts to validating nanosheet and stacked device architectures and full back-side power delivery process flows, leveraging Lam Research's Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and Aether dry photoresist.

Conventional EUV lithography relies on chemically amplified wet photoresists, which struggle to meet the precision demands of High NA EUV systems. In contrast, Aether uses a vapor-deposited, plasma-developed dry photoresist. Its metal-organic composition absorbs 3–5× more EUV light than traditional carbon-based resists, reducing the dose required per wafer exposure and enabling single-print patterning at advanced nodes without costly multi-patterning. In January 2026, Lam Research revealed that Aether had been selected by a leading memory manufacturer for advanced DRAM production, though the company did not disclose the customer.

This collaboration aims to reliably transfer High NA EUV patterns onto actual device layers with high yield, accelerating industry adoption for next-generation interconnects and device patterning. Aether's dry resist process improves pattern fidelity by reducing steps between lithography and etch, lowering the risk of pattern degradation at fine geometries.

Meanwhile, nanosheet transistors increase drive current by stacking multiple thin silicon layers rather than enlarging device dimensions. The teams will build and validate complete process flows for nanosheet and stacked devices, along with back-side power delivery, which powers wafers from the back, freeing front-side interconnects for signal routing.