TSMC Angstrom-Node Leap Outpaces Samsung and Intel

According to TSMC, the company unveiled its latest A13 process technology at its Annual North America Technology Symposium held on April 22 (U.S. West Coast time) in Santa Clara, California, presenting a new milestone in advanced semiconductor manufacturing aimed at accelerating AI, high-performance computing (HPC), and mobile applications.

TSMC highlighted that the A13 node delivers a smaller chip area, improved energy efficiency, and higher performance compared with previous-generation technologies. It is positioned as part of the company’s next-generation angstrom-era roadmap, alongside the previously introduced A14 platform. Both the A13 and the enhanced A12 nodes are scheduled for volume production in 2029.

The company also disclosed that the A13 process is designed with full backward compatibility to A14 design rules while enabling a 6% area reduction. This allows customers to more easily migrate existing designs to the latest nanosheet transistor architecture without significant redesign effort. Through design-technology co-optimization, A13 further improves power efficiency and performance, reinforcing its role in next-generation computing workloads.

In addition, TSMC outlined its extended roadmap beyond A14, introducing the A12 process technology. The A12 node integrates Super Power Rail (SPR) technology, enabling backside power delivery to support demanding AI and HPC workloads. Like A13, A12 is also planned for production in 2029.

During the event, TSMC Chairman and CEO C.C. Wei emphasized that customers are consistently focused on future innovation and expect reliable access to advanced technologies such as A13. He noted that TSMC’s goal is to ensure its most advanced manufacturing solutions are ready when customers require them for next-generation product designs, enabling timely mass production.

Wei further stated that TSMC continues to lead the industry in density, performance, and power efficiency, while continuously optimizing its processes to better support future customer needs. He reiterated the company’s commitment to remaining a trusted long-term technology partner.

Beyond A13 and A12, TSMC also shared updates on its N2 platform evolution, introducing the N2U process. Built on design-technology co-optimization, N2U delivers a 3%–4% performance improvement or 8%–10% power reduction compared with N2P, along with a 2%–3% increase in logic density. Leveraging the maturity and high yield of the N2 platform, N2U is positioned as a balanced solution for AI, HPC, and mobile applications, with mass production expected in 2028.

With this expanded roadmap covering A14, A13, A12, and N2U, TSMC continues to strengthen its leadership in advanced semiconductor process technology, reinforcing its position in enabling next-generation AI-driven computing ecosystems.