TSMC Builds CoPoS to Reinforce Packaging Edge
According to industry sources, TSMC (TSMC) is accelerating its advanced packaging roadmap, expanding CoWoS (Chip-on-Wafer-on-Substrate) capacity while simultaneously advancing a more technically demanding panel-level solution known as CoPoS (Chip-on-Panel-on-Substrate). The strategy reflects the company’s effort to reinforce its leadership in high-performance semiconductor packaging through higher technological barriers and greater manufacturing scalability.
At its April 2026 earnings call, TSMC Chairman C.C. Wei publicly highlighted CoPoS for the first time, emphasizing that artificial intelligence (AI) demand continues to significantly outpace supply. He noted that the company is working to provide sufficient capacity at sustainable cost levels to support customer requirements across AI and high-performance computing applications.
Supply chain insights indicate that TSMC is applying strict control over its CoPoS ecosystem. Equipment and materials partners are reportedly required to sign collaboration agreements designed to prevent leakage of proprietary development know-how, with certain technologies expected to remain exclusively supplied to TSMC for several years following ramp-up.
CoPoS is widely regarded as the next evolution of CoWoS. The key technological shift lies in moving from traditional 12-inch round wafers to large square panels as redistribution layer (RDL) carriers. This transition is expected to improve area utilization efficiency to as high as 95%, enabling significantly more chip placements per package and potentially delivering multiple times the throughput of CoWoS. However, the approach introduces substantial technical challenges, particularly in managing warpage control and process uniformity at large panel scale.
Current pilot development is reportedly taking place at TSMC’s internal facility in Longtan under TSMC’s advanced packaging division. Pilot equipment procurement is expected around Q3 2027, while volume production is not anticipated until approximately 2030.
To strengthen its competitive position against rivals such as Intel (Intel) and Samsung Electronics (Samsung Electronics), TSMC is also planning two advanced packaging facilities in Arizona, United States. One of the planned sites, P2, is expected to potentially host CoPoS-related production lines in the future.
In preparation for the technology ramp-up, TSMC has already outlined its 2025 ecosystem roadmap, involving global semiconductor equipment leaders including KLA Corporation, Tokyo Electron, and Applied Materials, alongside multiple Taiwan-based advanced equipment and process solution providers.
Industry participants note that TSMC’s strategy is increasingly focused on building a tightly controlled advanced packaging ecosystem. While this approach may strengthen technological integration and supply stability, uncertainties remain regarding whether exclusive supply arrangements can be fully maintained as global competitors continue to expand their AI packaging capabilities and attract key technology partners.
In parallel, some emerging technologies—such as Balance Film solutions developed by ShanTai Technology—have reportedly passed internal validation tests. However, industry observers suggest that commercial commitments may still be influenced by competing demand from other semiconductor players, leaving long-term exclusivity agreements uncertain.
