TSMC CoPoS to Launch in 2028, NVIDIA Feynman Adopts

According to the latest analysis from TF International Securities analyst Ming-Chi Kuo, TSMC’s next-generation advanced packaging platform, CoPoS (Chip-on-Panel-on-Substrate), is expected to enter mass production in the second half of 2028. As demand for AI computing power continues to surge, advanced packaging has become a key competitive area in the semiconductor industry. CoPoS is designed to address the cost and scalability challenges of packaging ultra-large AI chips and is considered a strategic evolution of TSMC’s existing CoWoS (Chip-on-Wafer-on-Substrate) technology.

The core concept of CoPoS is to transition advanced packaging from a traditional wafer-level approach to a panel-level architecture. By replacing the conventional round silicon interposer with a square glass panel, the technology can significantly improve material utilization efficiency, increasing it from approximately 65% to more than 90%. This improvement is expected to reduce the cost of large-scale AI chip packaging while supporting increasingly complex chip designs.

CoPoS is primarily aimed at ultra-large package solutions exceeding 9.5 times the reticle size limit. In the future, the platform could potentially support advanced package designs exceeding 14 reticle areas, providing greater flexibility for next-generation AI accelerators and high-performance computing applications.

Reports indicate that NVIDIA’s planned next-generation AI chip, “Feynman,” could become one of the first products to adopt CoPoS technology, with its expected production schedule closely aligning with the platform’s development timeline.

Regarding industry discussions about whether glass substrates will replace ABF materials, Kuo clarified that glass and ABF films are complementary technologies rather than substitutes. The CoPoS glass core substrate is expected to feature a three-layer “sandwich” structure:

Core layer: A glass core provides mechanical support and vertical electrical connectivity.

Build-up layers: Both sides of the glass core are covered with ABF (ABF-GCP) layers, which enable fine circuit routing and electrical insulation.

For mass production, CoPoS is expected to use large glass panels measuring approximately 510 x 515 mm. However, manufacturing will face significant technical challenges, including TGV (Through Glass Via) formation, copper filling, and metallization processes.

Kuo also highlighted three common misunderstandings about CoPoS technology. First, glass is not used as an interposer; signal interconnection is achieved through chip-side RDL (Redistribution Layer) together with TGV and ABF structures in the glass core substrate. Second, glass does not replace ABF, as both materials work together within the package architecture. Third, chips are not placed directly on glass but are connected to the ABF build-up layer on the surface of the glass core substrate.

Beyond increasing package size, CoPoS could also provide an ideal platform for integrating Co-Packaged Optics (CPO), enabling closer integration of optical components such as optical engines and couplers. The advancement of CoPoS technology is expected to further strengthen TSMC’s position in advanced packaging, with its technological impact potentially extending through 2032.