Intel EMIB-T Advances, Costs 50% Less Than TSMC CoWoS

According to industry reports, Intel’s EMIB-T advanced packaging technology has achieved a yield rate of more than 90% and is expected to enter mass production in 2027. The technology is reportedly capable of reducing packaging costs to about half of TSMC’s CoWoS solution, attracting significant industry attention. Intel has also secured an advanced packaging order from MediaTek, while major technology companies including Broadcom and Meta are evaluating potential adoption.

As demand for advanced packaging capacity continues to exceed supply, industry observers believe Intel’s EMIB-T technology is unlikely to directly replace TSMC’s CoWoS solution in the near term. Instead, it may help relieve capacity pressure by providing an additional option for customers. However, the technology could strengthen Intel’s competitiveness in advanced packaging and foundry services, supporting its long-term goal of competing more effectively with TSMC.

Reports indicate that Intel’s advanced packaging back-end manufacturing yield has exceeded 90%, reaching a level suitable for mass production. However, Intel has not officially disclosed yield figures and has not commented on the market reports.

According to foreign media reports, Intel’s EMIB-T packaging technology could cost approximately 50% less than TSMC’s CoWoS, mainly because it does not require the use of expensive large-area silicon interposers. Instead, EMIB-T uses Intel’s embedded bridge technology to achieve high-density chip-to-chip connections with a more cost-efficient approach.

Intel’s EMIB-T technology has reportedly secured a key ASIC packaging project from MediaTek. During its April earnings conference, MediaTek revealed that it was investing in two advanced packaging technology solutions and working closely with partners to provide customers with high-performance and cost-effective solutions.

MediaTek later confirmed that it would help customers leverage both CoWoS and EMIB-T technologies to develop high-performance ASICs with extremely large chip sizes, indicating that Intel’s advanced packaging solution has become part of its future packaging ecosystem.

Intel previously announced that it could independently provide advanced packaging services to external customers. Its EMIB 2.5D packaging technology uses small embedded silicon bridges combined with multi-layer interconnects to replace the large silicon interposers commonly used in competing solutions. The technology supports high-bandwidth memory (HBM) integration and is designed for AI applications requiring high bandwidth, low latency die-to-die connections, flexible chiplet configurations, and reduced manufacturing complexity.

According to Intel’s technical information, the EMIB-T variant enhances the EMIB 2.5D packaging platform by incorporating through-silicon via (TSV) technology to improve vertical power delivery and enable easier migration from other packaging architectures. Industry reports suggest that Intel’s advanced packaging capabilities are increasing interest in its foundry business.

By enabling designers to combine 2D, 2.5D, and 3D chip integration approaches, Intel’s EMIB technology aims to optimize system-level performance, power efficiency, bandwidth, and cost, positioning it as a potential alternative solution for next-generation AI chips and high-performance computing applications.