Cadence Announces Successful Tape-out of Its Advanced Packaging IP Based on TSMC's 3nm Process Technology

Dutch Cadence, a leading electronic design automation company, has announced the successful tape-out of its Cadence® 16G UCIe™ 2.5D advanced packaging IP based on TSMC's 3nm (N3E) process technology. This IP, which utilizes TSMC's 3DFabric™ CoWoS-S silicon interposer technology, provides high bandwidth density, efficient low power performance, and low latency, making it ideal for applications that require high computing power.

As the industry shifts towards system-in-package (SiP) chiplets driven by artificial intelligence/machine learning (AI/ML), mobile, automotive, storage, and network applications, chiplet-to-chiplet communication becomes increasingly important. The Cadence UCIe IP provides an open standard for communication between chiplets.

Cadence is currently working with many customers, and the UCIe advanced packaging IP for testing N3E chips is now available for use. This pre-validated solution enables quick integration and saves customers time and effort.

The complete solution includes the UCIe advanced packaging PHY and controller, which simplify chiplet solutions and have reusable bare-die capability. The UCIe standard packaging PHY is designed to support die-edge bandwidth densities of 5Tbps/mm or more, while the UCIe controller is a soft IP core that can be synthesized at multiple technology nodes and offers a variety of options for different target applications, supporting flow, PCIe®, and CXL protocols.

"We are pleased to congratulate Cadence on achieving this milestone in advanced packaging test chip tape-out using die-to-die interconnect based on the UCIe 1.0 specification," said Dr. Debendra Das Sharma, Chairman of the UCIe Alliance. "The progress of member companies in IP (extensions) and VIP (testing) is an important part of this ecosystem. Along with the work of the UCIe Working Group, the industry will continue to see new chiplet designs based on open industry standards entering the market, promoting interoperability, compatibility, and innovation."

"Cadence has been a pioneer in chiplet system solutions and will continue to push the performance and efficiency limits of various multi-chiplet applications in advanced nodes and packaging architectures," said Sanjive Agarwala, Global Vice President and General Manager of Cadence's IP Business. "We believe that coordinating industry interconnect standards is critical, and the UCIe IP can serve as a bridge to provide an open chiplet connectivity standard for large system-level chips that meets or exceeds the maximum mask limit. The tape-out of the UCIe advanced packaging based on TSMC's N3E process is a key milestone and commitment to providing an open chiplet connectivity standard for customers."