TSMC Boosts 2nm Trial Production with AI, Targets Apple and NVIDIA

According to a report from Taiwan's Economic Daily News, TSMC has recently commenced pre-production work for its 2nm technology, employing cutting-edge AI systems to enhance energy efficiency and expedite the trial production process. In the initial stages of 2nm development, TSMC will establish a small-scale trial production line in the Hsinchu Science Park, with a target of producing nearly a thousand wafers this year. Once the trial production is successful, TSMC will transition to the completed Fab 20 in the Tainan Science Park to continue with risk production trials in 2024, followed by mass production in 2025.

Major companies such as Apple and NVIDIA are expected to become TSMC's first customers for 2nm mass production, according to reports. TSMC, however, has declined to comment on these rumors, emphasizing that the progress of its 2nm technology development is on track, with mass production anticipated in 2025.

On June 4th, TSMC reiterated its refusal to comment on the rumors and highlighted the smooth progress of its 2nm technology development, reaffirming the projected timeline for mass production in 2025. Insider sources revealed that TSMC has also begun reallocating engineers to the research and development facilities in the Hsinchu Science Park to prepare for the pre-production work of 2nm technology. It is estimated that a research and development team of over a thousand people will be assembled at Fab 20 in the Tainan Science Park, leading the global production of 2nm technology. TSMC's most advanced 2nm production base will initially be established at Fab 20, which is part of a four-phase plan, and will subsequently expand to the Taichung Science Park, totaling six phases of engineering.

Currently, TSMC's advanced semiconductor technology in mass production utilizes the FinFET transistor architecture. The roadmap reveals that the next generation will employ the GAAFET (Gate-All-Around Field-Effect Transistor) architecture with a nanosheet structure, suitable for processes below 3nm. TSMC has stated that the upcoming 2nm N2 process node will utilize the GAAFET structure. As previously reported, ASML is in the process of developing the High-NA EUV lithography machine, and it is expected that TSMC will be the first to acquire this machine in 2024 for the production of GAAFET-based chips using the 2nm process.