Synopsys AI-Driven Analog Design for TSMC N2/N3E/N4P

Synopsys has recently unveiled the integration of its advanced analog design migration flow into TSMC's cutting-edge N4P, N3E, and N2 processes. As a pivotal component of Synopsys' Custom Design Platform, this analog design migration flow features innovative machine learning-based schematic and template-based layout migration solutions, streamlining the overall analog design migration process. Through the incorporation of parasitic-aware and AI-driven optimization techniques, this solution minimizes manual iterations in the analog design tuning process, ensuring alignment with stringent design specifications. Developers can leverage this streamlined workflow to optimize their designs on emerging process nodes, resulting in significant time and resource savings.

The release of interoperable Process Design Kits (iPDK) tailored for TSMC's N4P, N3E, and N2 processes marks a crucial milestone, allowing developers to kickstart their projects earlier and vastly enhance design efficiency. By adopting iPDK, mutual customers gain access to leading global design tools, simplifying development workflows and reducing Turnaround Time (TAT). Furthermore, Synopsys, in collaboration with Ansys and Keysight, introduces an open RFIC reference flow tailored for TSMC's N4P RF FinFET process. This collaborative effort facilitates partners in expediting RF design processes. The open RF design flow serves as a valuable resource for RF SoC developers, enabling them to navigate the delicate balance between performance, power efficiency, and time-to-market considerations.