RISC-V Server Chip: 4nm, 192 Cores, Beats AMD Epyc 9754

On November 9th, Ventana Micro Systems, a leading RISC-V server chip design firm, unveiled its highly anticipated second-generation server CPU, the Veyron V2, during the prestigious 2023 RISC-V Summit. Boasting significant enhancements across instruction extensions, core design, interconnect standards, and process technology, the Veyron V2 positions itself as a formidable competitor, with performance claims surpassing AMD's Epyc 9754, marking it as a potential powerhouse in the RISC-V server CPU landscape. Ventana's innovative offering extends beyond the CPU realm, allowing clients to seamlessly integrate custom accelerators into their System-on-Chip (SoC) blueprints.

Building on their groundbreaking release in December 2022, Ventana introduced the world to the Veyron V1, the inaugural server CPU based on the RISC-V architecture. Crafted with precision on a 5nm process, featuring Ventana's high-performance RISC-V core, an 8-stage pipeline design, out-of-order execution, and scalable up to an impressive 192 cores across multiple clusters, the Veyron V1 set the bar high. Its advanced features, including robust side-channel attack mitigation, IOMMU, Advanced Interrupt Architecture (AIA), and comprehensive RAS capabilities, positioned it as a potential contender to outperform AMD EPYC 7763.

Despite the Veyron V1's slated release in the latter half of the current year, customer adoption remains pending, prompting Ventana's strategic move to introduce the Veyron V2.

Travis Lanier, Vice President of Marketing and Product at Ventana, highlighted the Veyron V2's incorporation of the latest updates from the RISC-V specification, notably the RVA23 feature set—a cutting-edge instruction set architecture configuration introduced in 2023. The Veyron V2 not only aligns with the RISC-V Input Output Memory Management Unit (IOMMU) specification but also supports the UCIe interconnect standard, catering to the evolving needs of compact chip designs.

Ventana has also added a 512-bit vector processing unit to its core using the RISC-V Vector Extension Specification, along with AI matrix expansion capabilities. Additionally, support for the DSA and Chiplet standard UCIe enables faster chip manufacturing and allows customers to add FPGA and ASIC accelerators, providing flexibility while reducing entry barriers by allowing the use of smaller IP blocks using UCIe and I/O hubs to build packages.

Specifically regarding the core configuration of Veyron V2, it is based on TSMC's 4nm process, continuing the 8-stage pipeline design with out-of-order execution support. It has a maximum frequency of 3.6GHz, an increase in the number of cores per cluster to 32 compared to the previous generation, and can be expanded to a maximum of 192 cores with multiple clusters. The cache size has also been increased to 1MB L2 cache per core and 128MB shared L3 cache at the cluster level.

Lanier claims that all the new upgrades in Veyron V2 result in an almost 40% performance improvement compared to the previous generation. Official performance projections indicate that the 192-core Veyron V2 outperforms AMD's high-end server chip Epyc 9754.

Ventana will also provide a 1U server reference design based on Veyron V2, featuring four 128-core chips and 12 channels of DDR5-5600 memory. The small chips include UCI Express interconnects and an I/O interface, allowing them to be placed in server CPU sockets.

According to reports, Veyron V2 is expected to enter production in the third quarter of 2024, with the UCIe 1.1 PHY for interconnecting the smaller chips also expected to launch around the same time.