TSMC's 2030 Goal: 1nm Tech, 1 Trillion+ Transistors

In a recent update reported by Tom's Hardware, TSMC, a leading semiconductor manufacturing company, has unveiled its forward-looking roadmap at the IEDM conference. Notably, TSMC is set to launch the groundbreaking 1nm A10 process in 2023, intending to integrate an impressive 200 billion transistors on a singular chip. This achievement is facilitated by leveraging cutting-edge packaging technologies, with the ultimate objective of achieving the integration of a staggering 1 trillion transistors within a single package.

Delving into the specifics of TSMC's strategic plan, the company is slated to commence mass production of the 2nm N2 process in 2025, followed by the N2P process around 2026. These processes will incorporate innovative materials such as new channel materials, EUV, Metal Oxide ESL, Self-Aligned Lines w/Flexible Space, Low-Damage/Hardened Low-K, and novel copper filling technologies. The outcome is anticipated to be the integration of over 100 billion transistors on an individual chip, complemented by the application of advanced 3D packaging technology for the integration of over 5,000 transistors within a single package.

Post-2027, TSMC has outlined plans for the mass production of the 1.4nm A14 process, followed by the 1nm A10 process in 2030. The latter aims to integrate over 200 billion transistors on a single chip, with advanced 3D packaging technology pushing the envelope to over 1 trillion transistors within a single package.

Despite the recent deceleration of Moore's Law, TSMC maintains confidence in the continuous enhancement of semiconductor chips over the next five to six years. This optimism is anchored in the introduction of 2nm, 1.4nm, and 1nm processes, promising advancements in performance, power efficiency, and transistor density.

The semiconductor landscape is poised to witness the emergence of more intricate single-chip designs, exemplified by Nvidia's GH100, which currently boasts 800 billion transistors. TSMC foresees the advent of even more sophisticated single-chip designs surpassing the 1 trillion transistor mark. However, TSMC acknowledges that the associated processes will become more intricate, leading to heightened costs. Consequently, many industry players may opt for multi-chip packaging designs, as exemplified by AMD's MI300X and Intel's Ponte Vecchio, which comprise several dozen chips.