TSMC SoIC Capacity to Triple in 2024!

On January 18th, TSMC is reportedly set to enhance its SoIC production capacity this year. Anticipated by the end of 2023, the monthly production is expected to surge from approximately 2,000 pieces to a range of 5,000-6,000 pieces, aligning with the growing demands in Artificial Intelligence (AI) and High-Performance Computing (HPC) sectors.

TSMC's SoIC represents a pioneering high-density 3D chip stacking technology, leveraging the Chip on Wafer (CoW) packaging technique for heterogeneous integration of chips with varying sizes, functionalities, and nodes. Production takes place at the AP6 facility in Zhunan. Initial projections for this year's monthly production capacity aimed at 3,000-4,000 pieces, but recent adjustments have pushed the target to 5,000-6,000 pieces, with an ambitious goal to double the capacity by 2025.

CoWoS (Chip-on-Wafer-on-Substrate) stands as a mature technology with a 15-year development history, and TSMC envisions achieving a monthly production capacity of 30,000-34,000 pieces by year-end. TSMC strategically positions its SoIC as a flagship product dominating the global 3D stacking technology landscape. Reports suggest that AMD's MI300 flagship product integrates SoIC with the CoWoS process, enhancing AMD's competitive edge in the AI server domain and establishing TSMC's SoIC as a distinguished offering.

Significantly, Apple, a key client of TSMC, exhibits a keen interest in SoIC. Ongoing trials involve SoIC paired with Hybrid Molding technology, with mass production anticipated between 2025 and 2026. The incorporation of SoIC in products such as Mac and iPad is expected to yield cost advantages over existing solutions.

Regarding TSMC's other major client, NVIDIA, while their current high-end products predominantly use CoWoS packaging technology, industry experts foresee a future integration of SoIC technology. Fueled by demand from AMD, Apple, and NVIDIA, TSMC's expedited expansion of SoIC production signals a secure future, with confirmed orders for advanced chip manufacturing and packaging already secured.