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Samsung: Entering the 3D DRAM Era Post-2025

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Samsung: Entering the 3D DRAM Era Post-2025

According to a recent update from Semiconductor Engineering, Samsung Electronics has announced its forthcoming entry into the era of 3D DRAM post-2025, as unveiled during the Memcon 2024 semiconductor industry conference.

Samsung's projection suggests a shift in the DRAM industry towards sub-10nm processes by 2030, posing challenges to current design paradigms. In response, various manufacturers are exploring innovative 3D DRAM designs to optimize memory performance.

Samsung showcased two cutting-edge 3D DRAM technologies: Vertical Channel Transistor and Stacked DRAM. The former employs a vertical channel orientation, reducing component size significantly albeit requiring enhanced etching precision.

Stacked DRAM, on the other hand, capitalizes on Z-axis space, enabling a higher storage unit density within a smaller footprint. Single-chip capacities are expected to exceed 100G. Analysts anticipate substantial growth in the 3D DRAM market, with projections reaching trillions by 2028.

In a bid to maintain competitiveness, Samsung has inaugurated a new 3D DRAM research laboratory in Silicon Valley earlier this year, dedicated to pioneering advanced memory solutions.


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