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Kioxia Plans 1000-Layer 3D NAND Flash by 2031!

2024-04-07 16:18:55Mr.Ming
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Kioxia Plans 1000-Layer 3D NAND Flash by 2031!

According to reports from Xtech Nikkei, Hidefumi Miyajima, Chief Technology Officer (CTO) of Kioxia, a leading Japanese manufacturer of storage chips, has announced ambitious plans to commence large-scale production of 3D NAND Flash chips boasting over 1000 layers by 2031.

During his presentation at the 71st Spring Meeting of the Japan Society of Applied Physics held at Tokyo City University, Miyajima discussed the technological challenges and solutions involved in achieving this significant milestone in 3D NAND devices.

Increasing the number of active layers within 3D NAND Flash devices stands as a critical strategy for enhancing NAND Flash density. Consequently, major players in the 3D NAND Flash industry continuously work to introduce new process nodes approximately every 1.5 to 2 years to realize this objective. Each advancement brings forth unique challenges, demanding manufacturers to elevate layer counts while simultaneously reducing NAND Flash unit dimensions both horizontally and vertically. This iterative process necessitates the adoption of novel materials at each new node, representing a significant research and development challenge.

Presently, Kioxia's eighth-generation BiCS 3D NAND Flash device stands out with an impressive 218 active layers and a 3.2 GT/s interface, initially introduced in March 2023. This iteration introduces the innovative CBA (CMOS Bonding to Array) architecture, which involves the separate fabrication of 3D NAND Flash unit array wafers and I/O CMOS wafers using state-of-the-art process technologies, subsequently bonding them together. The outcome is a product with augmented bit density and enhanced NAND I/O speed, ensuring the memory can be harnessed to develop top-of-the-line SSDs.

Despite this progress, Kioxia and its manufacturing partner, Western Digital, have yet to disclose specific details regarding the CBA architecture, including whether the I/O CMOS wafers encompass additional NAND peripheral circuits such as page buffers, read amplifiers, and charge pumps. Through the discrete production of storage units and peripheral circuits, manufacturers can leverage the most efficient process technologies for each component. As the industry embraces methodologies like string stacking, manufacturers stand to gain further advantages, with string stacking poised to be employed in 1000-layer 3D NAND Flash.

It's noteworthy that Samsung has also announced intentions to achieve mass production of 1000-layer 3D NAND Flash in the foreseeable future.

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