TSMC Advances 2nm, Kaohsiung Factory Prepares

Top-tier semiconductor manufacturer TSMC recently announced plans to establish a cutting-edge 2nm production facility in the United States, drawing significant interest in the ongoing expansion efforts in Taiwan, particularly in Baoshan and Kaohsiung.

Recent industry updates reveal that TSMC's Baoshan 2nm production is progressing steadily as per schedule, while the Kaohsiung facility is accelerating its pace, with installation set to commence by year-end and initial production expected to begin in early 2026. Both facilities aim to achieve a monthly production capacity of approximately 30,000 to 35,000 wafers, with a combined capacity exceeding 100,000 wafers by 2027.

Sources within the semiconductor supply chain indicate that TSMC's 2nm production bases are strategically located in Hsinchu and Kaohsiung. Baoshan Phase 2 is scheduled to begin equipment installation in the second quarter, with plans for a "mini line" by year-end and mass production by the fourth quarter of the following year. Similarly, Kaohsiung's facility is gearing up for installations by the end of this year, targeting mass production in the first half of 2026.

Post the commencement of mass production at both facilities, TSMC plans to ramp up capacity, aiming for a combined output of 110,000 to 120,000 wafers by 2027. These facilities will produce cutting-edge 2nm chips and N2P chips with back-side power supply. Additionally, mass production of the next-generation 1.4nm (A14) chips is anticipated to begin in the latter half of 2027, potentially at TSMC's Taichung facility.

In terms of clientele, major players like Apple and Intel have shown keen interest, with other industry giants like AMD, Nvidia, and MediaTek expected to follow suit. The timeline suggests that the first terminal product utilizing TSMC's 2nm technology is likely to hit the market by 2026.

During the recent TSMC Technology Symposium, it was revealed that back-side power supply solutions for N2 hold significant promise for High-Performance Computing (HPC) applications. These solutions are expected to enhance speed by 10% to 12% and logic density by 10% to 15%. The target is to introduce back-side power supply in the second half of 2025, followed by mass production in 2026.