TSMC Unveils A16 Chip Tech for 2026 Production

On April 24, TSMC held its North America Technology Symposium in Santa Clara, California, where it unveiled its latest process technology, advanced packaging technology, and 3D integrated circuit (3D IC) technology. This cutting-edge semiconductor technology is expected to drive the next generation of AI innovation.

At the symposium, TSMC introduced its A16 (1.6nm) technology, which integrates advanced nanosheet transistors with a new backside power rail solution to significantly enhance logic density and performance. Mass production of this technology is anticipated to begin in 2026. TSMC also presented its System-on-Wafer (TSMC-SoW™) technology, an innovative solution that delivers groundbreaking wafer-level performance benefits to meet future AI requirements for large-scale data centers.

· TSMC A16 Technology

The A16 technology combines TSMC's Super PowerRail architecture with nanosheet transistors and is expected to enter mass production in 2026. The Super PowerRail technology relocates the power network to the back of the wafer, freeing up more space on the front for signal network layouts. This increases logic density and performance, making A16 suitable for high-performance computing (HPC) products with complex signal routing and dense power networks.

TSMC states that compared to the N2P process, the A16 offers

an 8-10% speed increase at the same operating voltage (Vdd) and a 15-20% reduction in power consumption at the same speed. Additionally, chip density improves by up to 1.10 times, supporting data center products.

· NanoFlex Technology

TSMC's upcoming N2 technology will be paired with TSMC NanoFlex technology, showcasing TSMC's new breakthroughs in design technology and optimization. NanoFlex provides chip designers with flexible N2 standard elements, which serve as the basic building blocks for chip designs. Lower-height elements save area and offer higher power efficiency, while higher-height elements maximize performance. Clients can optimize the mix of high and low elements within the same memory block design, balancing power consumption, performance, and area efficiency.

· N4C Technology

TSMC also announced the introduction of advanced N4C technology to cater to a broader range of applications. N4C builds on the N4P technology and reduces die cost by up to 8.5%, with low adoption barriers. Mass production is expected in 2025. N4C offers cost-effective and area-efficient foundational IP and design rules fully compatible with the widely adopted N4P, enabling customers to transition seamlessly to N4C. This leads to smaller die sizes and improved yield, offering a cost-effective upgrade to TSMC's next-generation advanced technology.

· CoWoS, System-on-Wafer, and System-level Chip

Additionally, TSMC introduced its System-on-Wafer (TSMC-SoW™) technology, which provides revolutionary wafer-level performance benefits for large-scale data center AI needs. At the same time, TSMC's System Integration Chip (SoIC) has become the leading solution for 3D chip stacking, with customers increasingly adopting CoWoS in combination with SoIC and other elements to achieve final System-in-Package (SiP) integration.

TSMC's first mass-produced SoW product utilizes integrated fan-out (InFO) technology focused on logic chips, while the stacked chip version using CoWoS technology is expected to be ready by 2027. This integration can combine SoIC, HBM, and other components to create a powerful wafer-level system comparable to data center server racks or even entire servers.

· Silicon Photonics Integration

TSMC is developing Compact Universal Photonic Engine (COUPE™) technology to support the explosive data transmission growth driven by the AI boom. COUPE uses SoIC-X chip stacking technology to stack electronic dies on top of photonic dies, providing the lowest resistance and higher energy efficiency compared to traditional stacking methods. TSMC plans to complete COUPE validation supporting small form-factor pluggable (SFP) connectors by 2025 and then integrate CoWoS packaging to become Co-Packaged Optics (CPO) in 2026, bringing optical connections directly into packaging.