Samsung and SK Hynix to Use 1c DRAM for New HBM4

According to recent industry reports from ZDNet Korea, leading memory chip manufacturers Samsung and SK Hynix are preparing to develop the next generation of High Bandwidth Memory (HBM4) utilizing the advanced 1c process DRAM.

Initially, Samsung planned to use its 1b DRAM (10nm-class 5th generation DRAM) for HBM4 production, which was set to begin in May of the previous year. Their existing HBM3E products are based on 1a DRAM. However, recent developments indicate that Samsung's 1b DRAM did not meet the qualification standards for NVIDIA’s latest AI GPUs, such as the Hopper and Blackwell series. This setback has prevented Samsung from securing NVIDIA’s HBM3E orders, prompting a shift to the more advanced 1c DRAM for their forthcoming HBM4.

Another critical reason for this transition is Samsung's acknowledgment that their 1b DRAM lags behind SK Hynix in terms of power efficiency. As a result, Samsung plans to deploy 1c DRAM for both 12-Hi (12-layer stack) and 16-Hi (16-layer stack) HBM4 products. The first production line for 1c DRAM is expected to be operational by the end of 2024, with a projected monthly capacity of approximately 3000 wafers. Some sources even suggest that mass production could commence by mid-2025, although this has not been confirmed.

Samsung and SK Hynix are both striving to set the standard for the next generation of HBM4 memory. While both companies are initially focusing on the 1b DRAM process, Samsung is leveraging 3D packaging technology and aiming for up to 16-Hi stacks to significantly enhance VRAM capacity and memory bandwidth. In contrast, SK Hynix is collaborating with TSMC to implement new packaging techniques for its HBM4 solutions.

At TSMC’s 2024 European Technology Symposium, it was revealed that the transition of HBM4 memory from a 1024-bit interface to a 2048-bit interface involves substantial complexity. The new base chips will be manufactured using the N12 and N5 process nodes.

TSMC’s Senior Director of Design and Technology Platform stated, “We are collaborating with key HBM memory partners—Micron, Samsung, SK Hynix—to achieve full-stack HBM4 integration on advanced nodes. The cost-effective N12 FFC+ base chip can meet HBM performance standards, while the N5 base chip can deliver more logical performance at HBM4 speeds with significantly lower power consumption.”

Additionally, TSMC is partnering with EDA companies like Cadence, Synopsys, and Ansys to validate HBM4 channel signal integrity, IR/EM, and thermal accuracy. The new base chips will utilize CoWoS technology (including the recently announced CoWoS-L and CoWoS-R packaging) to produce memory products with up to 16-Hi stacks, incorporating a new channel signal integrity process. The use of the 5nm node is expected to offer advantages in power consumption, performance, and density, paving the way for the release of next-generation HBM4 memory products for future GPU accelerators.