AMD CEO Lisa Su: 100x Chip Efficiency in 3 Years!

At the recent ITF World 2024 conference hosted by the Interuniversity Microelectronics Centre (IMEC) in Belgium, AMD Chair and CEO Dr. Lisa Su received the prestigious IMEC Innovation Award. This honor recognizes her remarkable contributions to innovation and leadership in the technology industry, placing her alongside previous recipients such as Gordon Moore and Bill Gates.

In her acceptance speech, Dr. Su highlighted AMD's ambitious "30×25" initiative, aiming to boost computing efficiency by 30 times compared to 2014 levels by the year 2025. Additionally, she outlined an even more audacious target: achieving a 100-fold improvement in computing efficiency by 2026-2027. These goals are set to far exceed the average industry advancements.

As processors, GPUs, and other computing chips consume increasing amounts of power, AMD set a "25×20" goal in 2014 to enhance product efficiency by 25 times by 2020. Exceeding expectations, AMD achieved a 31.7-fold improvement. Building on this success, the "30×25" target is expected to be met as early as next year.

Dr. Su identified the primary challenge in improving computing efficiency as the immense computational power required for training and fine-tuning large AI models. This often necessitates thousands of GPU accelerators and significant power consumption, with demands continually growing.

To tackle this, AMD is enhancing efficiency through advancements in product architecture, manufacturing processes, packaging technologies, and interconnect technologies. Notable innovations include the 3nm Gate-All-Around (GAA) process and 2.5D/3D hybrid packaging techniques.

Dr. Su emphasized that AMD's flagship AI chip, the Instinct MI300X, exemplifies high efficiency. The MI300X features 153 billion transistors divided across 12 chiplets and integrates 24 HBM3 memory chips totaling 192GB.

In terms of CPU processors, the upcoming fourth-generation EPYC, set for release in 2024, showcases AMD's significant progress. Compared to the 1984 AM286 (a clone of the Intel 80286), manufacturing processes have advanced from 1.5 microns to 6/5 nanometers. The chip design has evolved from a single chip with 134,000 transistors to 13 chiplets containing 90 billion transistors. Core and thread count have increased from single-core/single-thread to 96 cores/192 threads. Operating frequency has risen from 20MHz to 3.5GHz, cache size has expanded from 16MB to 486MB, and die area has grown from 49 square millimeters to 1,240 square millimeters.