TSMC Develops CFET, Triples 3nm Capacity This Year

TSMC has successfully integrated different transistor architectures to develop Complementary Field-Effect Transistors (CFET) in their laboratory. According to TSMC's Senior Vice President and Co-COO, Kevin Zhang, CFET technology is set to be incorporated into advanced logic processes and next-generation logic technologies. TSMC's R&D team is also exploring new materials to enable a single logic chip to house over 200 billion transistors, driving continuous innovation in semiconductor technology.

TSMC has declared that the golden era of semiconductors is here. The future of artificial intelligence (AI) chips will heavily rely on TSMC's advanced logic technology and packaging solutions, with nearly 99% of AI chips expected to depend on TSMC's innovations. The company aims to deliver chips with higher performance and superior energy efficiency through ongoing technological advancements.

Kevin Zhang highlighted significant progress in the 2nm process, utilizing nanosheet technology. The conversion performance of nanosheets has reached 90%, with a conversion yield exceeding 80%. Mass production of this technology is anticipated by 2025.

Building on the 2nm process, TSMC has pioneered the A16 process technology, integrating exclusive backside power delivery techniques. This advancement enables chips to achieve 8-10% higher performance at the same speed and reduce energy consumption by 15-20% at the same area. TSMC plans to commence mass production of A16 in 2026, with the first chips targeted at high-performance computing (HPC) for data centers.

Additionally, TSMC has integrated both P-FET and N-FET transistors to create CFET architecture chips in the lab. This represents the next significant transistor architecture innovation following the 2nm nanosheet breakthrough. TSMC's research team will continue to explore integrating new transistor materials and innovative architectures, such as inorganic nanotubes or carbon nanotubes like Ws2 or WoS2. This effort aims to advance CFET into more sophisticated sub-nanometer processes while continually pushing the boundaries of transistor technology.

Huang Yuan-kuo, Senior Director overseeing 3nm production, indicated that TSMC plans to triple its 3nm capacity this year to meet strong demand. TSMC will also construct seven new factories, including those for advanced processes, advanced packaging, and mature processes, both domestically and internationally.

From 2020 to 2024, TSMC's capacity for 3nm, 5nm, and 7nm processes has grown at a compound annual growth rate (CAGR) of 25%. Special process technology has seen a CAGR of 10%, and automotive chip shipments have experienced a CAGR of approximately 50%. The proportion of special process technology in TSMC's mature products is also increasing, projected to rise from 61% in 2020 to 67% by 2024.

Between 2022 and 2023, TSMC built an average of five factories annually, but this year plans to increase that number to seven. This includes three wafer fabs in Taiwan (two 2nm fabs in Hsinchu and one in Kaohsiung), advanced packaging fabs in Taichung and Chiayi, and two overseas fabs (one in Kumamoto, Japan, and one in Dresden, Germany).