TSMC Advances Chip Packaging: From Wafer to Panel Level

According to industry sources, TSMC is investigating a groundbreaking chip packaging method that utilizes rectangular panel substrates instead of traditional round wafers. This advanced approach could significantly increase the number of chip sets that can be produced per wafer.

While this research is in its preliminary stages and may require several years to reach commercialization, it marks a major technological shift for TSMC. Previously, the use of rectangular substrates was considered too complex. The current rectangular substrates under trial measure 510mm x 515mm, offering over three times the usable area of the standard 12-inch circular wafers. This rectangular shape also reduces the unused edge area, optimizing space.

TSMC is known for its advanced chip stacking and assembly technologies, currently using 12-inch silicon wafers—the largest available. The company is expanding its capacity to meet the increasing demand for advanced chip packaging. Insiders reveal that the expansion of TSMC’s Taichung facility in Taiwan mainly supports Nvidia, while the Tainan facility expansion is geared towards Amazon and its chip design partner, Alchip.

In response to inquiries about this development, TSMC stated it is "closely monitoring advancements and developments in advanced packaging technologies, including panel-level packaging."

Once seen as a lower-tech segment of chip manufacturing, chip packaging has now become vital for sustaining semiconductor innovation. For instance, Nvidia’s AI computing chips, such as the H200 and B200, require not only the most advanced chip production but also TSMC’s cutting-edge CoWoS (Chip-on-Wafer-on-Substrate) packaging technology. Specifically, the B200 chipset leverages CoWoS to integrate two Blackwell graphics processing units with eight high-bandwidth memory (HBM) chips, resulting in faster data throughput and enhanced computational performance.

Mark Li, a semiconductor analyst at Bernstein Research, noted that TSMC might soon need to adopt rectangular substrates, as AI chipsets increasingly demand more chips per package.