Intel Panther Lake Revealed: 18A Process, 16 Cores, 12 Xe3 GPUs

On August 2 During Computex 2024 in June, Intel officially launched its new AI PC chip, Lunar Lake (Core Ultra 200 series), boasting a comprehensive computing power of up to 120 TOPS. Recently, more information has surfaced about Intel's next-generation AI PC chip for mobile platforms, the Core Ultra 300 series, set to debut in the second half of next year.

Intel has kept details about Panther Lake under wraps, but it has been revealed that Panther Lake will largely rely on Intel's own manufacturing processes. The critical computing cores will use Intel's 18A process technology, incorporating advanced techniques like hybrid bonding, wafer-to-wafer stacking, and advanced packaging with backside power delivery, known as PowerVia. In contrast, the current Lunar Lake generation cores are manufactured using TSMC's 3nm process.

The Intel 18A process node is Intel's most advanced technology in its roadmap of five process nodes over four years. Similar to Intel 20A, it utilizes the new RibbonFET gate-all-around transistor architecture and backside power delivery. The Intel 18A process is designed to offer architectural innovations and improved performance while continuing to reduce metal line widths, enhancing overall efficiency.

According to Intel CEO Pat Gelsinger, the Intel 18A process is expected to outperform TSMC's N2 (2nm) process. While the transistor densities of Intel 18A and TSMC N2 may appear similar, Intel's superior backside power delivery technology provides better area efficiency, potentially reducing costs and enhancing performance due to improved power delivery. This combination of efficient transistor density and advanced power delivery gives Intel 18A a competitive edge over TSMC N2. Additionally, TSMC's packaging costs are reportedly higher than Intel's, further positioning Intel's technology as a cost-effective alternative.

Recent updates from the Coreboot patch reveal additional information about the Panther Lake configurations. Panther Lake is expected to feature four distinct SKUs, each with a new performance core design and optimized efficiency cores.

The current Lunar Lake CPUs continue to utilize a hybrid core architecture, featuring Lion Cove P-core performance cores and Skymont E-core efficiency cores. The upcoming Panther Lake CPUs will introduce the new Cougar Cove P-Core for performance and Darkmont E-Core for efficiency, with potential upgrades to the LP E-core. The total CPU core count will increase to a maximum of 16 cores, representing a significant upgrade over previous generations.

On the GPU front, Lunar Lake is built on the Xe2 GPU architecture, codenamed “Battlemage,” with configurations that include 8 Xe 2 cores, 8 ray tracing units, XMX AI engines, and 8MB of dedicated cache. This setup delivers 67 GPU TOPS, real-time ray tracing, AI-based XeSS image enhancement, and comprehensive support from the Intel Arc software stack, offering a 50% improvement in graphics processing performance over the Meteor Lake series. The next-generation Panther Lake will adopt the new Xe3 GPU architecture, codenamed “Celestial,” which features up to 12 cores for enhanced graphical performance.

The Panther Lake lineup includes the following core configurations:

· PTL-H SKU #1: 4 P-Cores + 8 E-Cores + 0 LP-E Cores + 4 Xe3 Cores (TDP 45W)

· PTL-H SKU #2: 4 P-Cores + 8 E-Cores + 4 LP-E Cores + 12 Xe3 Cores (TDP 25W)

· PTL-H SKU #3: 4 P-Cores + 8 E-Cores + 4 LP-E Cores + 4 Xe3 Cores (TDP 25W)

· PTL-U SKU #1: 4 P-Cores + 0 E-Cores + 4 LP-E Cores + 4 Xe3 Cores (TDP 15W)

Comparatively, previous Meteor Lake processors featured up to 6 P-Cores, 8 E-Cores, and 2 LP-E Cores. Intel has optimized the IPC (Instructions Per Cycle) performance of each P-Core, allowing for a reduction of 2 P-Cores while adding 2 additional LP-E Cores. Intel notes that LP-E cores are more efficient for mobile tasks, and the Skymont E-cores provide significant IPC improvements.

Additionally, a leaked blueprint of the Panther Lake-H CPU reveals a structure composed of five tiles: Die 4: Compute Tile (114.3mm²), Die 1: Platform Controller Chip (PCD, 49.048mm²), Die 5: Graphics Compute Tile (54.73mm²), Die 2 and Die 3: Passive Tiles (24.154mm² and 9.83mm², respectively). The total core area of the chip is approximately 274.2mm², slightly larger than the Meteor Lake series, yet designed to deliver greater performance and efficiency.