TSMC to Launch 9-Mask CoWoS with 12 HBM4 Stacks by 2027

According to reports, TSMC recently announced plans to certify an ultra-large version of its CoWoS packaging technology by 2027. This new packaging solution will offer up to 9 mask layers and support 12 HBM4 memory stacks, addressing the highest-performance requirements for AI and HPC applications. The technology aims to enable chip designers to develop processors as small as the size of a hand.

Every year, TSMC introduces new process technologies to meet customer demands for improvements in PPA (Power, Performance, and Area). Some customers require even higher performance than what the current EUV lithography tools can provide, with their 858mm² mask size limitations. These customers have turned to TSMC's CoWoS multi-chip packaging solutions, with several iterations being introduced over the years.

The original CoWoS debuted in 2016 with a 1.5-mask chip package, evolving to today's 3.3-mask solution, which accommodates up to 8 HBM3 stacks in a single package. TSMC plans to roll out a 5.5-mask version between 2025 and 2026, capable of housing 12 HBM4 stacks. However, this will still be dwarfed by the company's ultimate CoWoS technology, which will support up to 9 masks in a system-in-package (SiP) configuration, capable of integrating 12 or more HBM4 stacks.

The 9-mask version of CoWoS, designed to offer up to 7722mm² of area for chips and memory, is expected to be certified by 2027, with adoption by high-end AI processors anticipated between 2027 and 2028. Additionally, companies utilizing TSMC's advanced packaging solutions may also take advantage of its System-on-Integrated-Chip (SoIC) technology for vertical stacking of logic, boosting transistor count and overall performance. With the 9-mask CoWoS, TSMC envisions placing 1.6nm chips on top of 2nm chips, enabling ultra-high transistor density.

However, these massive CoWoS packages present significant challenges. The 5.5-mask version will require substrates larger than 100x100mm, nearing the OAM 2.0 standard's size limits (102x165mm). The 9-mask version will require even larger substrates, measuring over 120x120mm. Such large substrates will affect system design and data center infrastructure, especially in terms of power supply and cooling. Each rack will require several hundred kilowatts of power, necessitating the use of liquid cooling and immersion techniques to effectively manage high-power processors.