TSMC Achieves 6% Yield Improvement in 2nm Process

TSMC is set to begin mass production of semiconductors using its cutting-edge 2nm (N2) manufacturing process in the second half of 2025. The company is currently focused on optimizing this technology to reduce variability and defect density, with the goal of enhancing yield rates. According to a recent statement from a TSMC employee, identified as Dr. Kim, the team has successfully improved the yield of test chips by 6%, potentially saving the company's clients billions of dollars.

While Dr. Kim did not disclose whether the yield improvements applied to SRAM or logic test chips, TSMC's 2nm process is expected to become available for multi-project wafer services in January 2025. This suggests that yield improvements are unlikely to be directly applied to the final prototypes of chips that will be produced using the 2nm process.

Improving the yield of SRAM and logic test chips is critical, as higher yield translates into significant cost savings for customers. Customers who pay for wafer production stand to benefit from more efficient manufacturing processes and reduced production costs.

TSMC's N2 process will introduce the company’s first fully-gate-all-around (GAA) nanosheet transistors, a technology expected to drastically lower power consumption, enhance performance, and increase transistor density. Notably, TSMC’s GAA nanosheet transistors are smaller than the 3nm FinFET transistors and offer improved electrostatic control while reducing leakage. This results in smaller, high-density SRAM bit cells that maintain performance without compromise. The design also improves threshold voltage regulation, ensuring reliable operation and enabling further miniaturization of logic transistors and SRAM units. However, TSMC must still master the challenge of achieving high yields with these novel transistors.

Forecasts suggest that chips produced using the N2 process will offer 25% to 30% lower power consumption compared to chips made at the N3E node, while delivering a 10% to 15% performance boost at the same transistor count and frequency. Moreover, transistor density will increase by 15% while maintaining the same speed and power as semiconductors produced at the N3E node.

TSMC is expected to begin high-volume production with its N2 process in late 2025, which will give the company ample time to further refine the technology, increase output, and reduce defect density, solidifying its leadership in semiconductor manufacturing.