TSMC 2nm Process: 35% Power Savings or 15% Performance Boost
Earlier this month, TSMC showcased additional insights into its groundbreaking N2 (2nm) manufacturing process at the IEEE International Electron Devices Meeting (IEDM). This new process node is set to deliver significant performance improvements, including a 24-35% reduction in power consumption or a 15% boost in performance at the same voltage. Additionally, the transistor density is 1.15 times higher than the previous generation 3nm process. These remarkable advancements are largely attributed to TSMC's innovative Gate-All-Around (GAA) nanosheet transistors, along with the N2 NanoFlex design technology and other enhancements unveiled during the IEDM.
The GAA nanosheet transistors offer design flexibility by enabling the adjustment of channel width to balance performance with power efficiency. Moreover, TSMC's N2 process introduces the N2 NanoFlex Design Technology-Computer-Aided Optimization (DTCO), which allows designers to develop ultra-compact units for enhanced power efficiency or high-performance units optimized for maximum output. The technology also supports six voltage threshold levels (6-Vt), spanning a range of 200mV, achieved using TSMC's third-generation Dipole Integration Technology, which integrates both n-type and p-type dipoles.
Innovations in both process and device levels not only improve transistor drive current through optimizations in sheet thickness, junctions, dopant activation, and stress engineering but also lower effective capacitance (Ceff) to achieve industry-leading energy efficiency. Overall, these improvements result in an approximately 70% and 110% increase in I/CV speed for n-type and p-type nanosheet transistors, respectively.
Compared to FinFET technology, N2's nanosheet transistors deliver superior performance per watt in the low supply voltage range of 0.5V to 0.6V. The process and device optimizations increase clock speeds by about 20%, while reducing standby power consumption by approximately 75% when operating at 0.5V. Furthermore, the integration of N2 NanoFlex and multiple threshold voltage (multi-Vt) options offers additional design flexibility for energy-efficient processors with high logic density.
The transistor architecture and DTCO benefits directly influence SRAM scalability, a challenge in recent advanced nodes. With N2, TSMC has achieved a record-breaking 38Mb/mm² 2nm SRAM density. In addition to this milestone, power consumption has been reduced. The GAA nanosheet transistors exhibit tighter voltage threshold variation (Vt-sigma), which enables the N2 process to lower the minimum operating voltage (Vmin) of high-current (HC) macros by about 20mV and high-density (HD) macros by 30-35mV. These advancements ensure stable yields and reliability for SRAM read and write functions at voltages as low as 0.4V.
Beyond the transistors, TSMC's N2 process incorporates new middle-of-line (MoL), back-end-of-line (BEOL), and far BEOL interconnects that reduce resistance by 20% while improving performance efficiency. The MoL now utilizes barrier-free tungsten interconnects, which decrease vertical gate contact (VG) resistance by 55% and increase the frequency of the ring oscillator by about 6.2%. Furthermore, the first metal layer (M1) can be created with a single EUV exposure, followed by an etching step (1P1E), streamlining complexity, reducing the number of masks, and improving overall process efficiency. TSMC notes that using EUV for M1 with 1P1E reduces standard cell capacitance by nearly 10% and saves several EUV masks. Additionally, N2 reduces metal (My) and via (Vy) resistance by 10%.
For high-performance computing (HPC) applications, N2 includes additional features such as the ultra-high-performance MiM (SHP-MiM) capacitors, which provide approximately 200fF/mm² capacitance. These capacitors help achieve higher maximum operating frequencies (Fmax) by mitigating transient voltage drop.
