Apple Delays 2nm Chip Use Until 2026

According to market reports, Apple is expected to be one of the first clients for Taiwan Semiconductor Manufacturing Company's (TSMC) 2nm process technology. However, due to cost considerations, the iPhone 17, featuring the A19 series processors, will not adopt this cutting-edge technology upon its launch in 2025. Instead, it is anticipated that the 2nm process will be applied to the A20 and A20 Pro processors in the iPhone 18 in 2026. By then, TSMC's monthly production capacity for this technology is projected to increase from the current trial production of 10,000 wafers to 80,000 wafers.

Industry insiders in the IC design sector suggest that the cost of producing a 3nm chip at a price of $20,000 per wafer—measuring 170 square millimeters—yields approximately 325 chips, with an average cost of $61 per chip. These chips are then priced at $122 per unit, yielding a 50% gross margin. However, for 2nm chips produced under similar conditions, the gross margin drops to just 32%. Additionally, reports indicate that TSMC's trial production yield for its 2nm process is currently at 60%, which, for profit-driven clients, may not meet the standards for placing orders just yet.

While TSMC has not disclosed specific pricing, industry sources suggest that the cost of a 2nm wafer could reach up to $30,000. As such, TSMC's monthly production must scale significantly to bring down costs. Morgan Stanley's latest report indicates that, at its current trial production level of 10,000 wafers per month, TSMC's capacity is still insufficient to meet demand. However, by 2025, TSMC anticipates its monthly output will reach 50,000 wafers, and by 2026, it is expected to reach 80,000 wafers—sufficient to meet orders from Apple and other companies.

Analysts predict that Apple may secure favorable pricing, with costs expected to fall around $26,000 per wafer. However, considering both the cost and chip architecture transition, Apple's A19 series processors and M5 chips for 2025 may still be produced using TSMC's N3P process. Compared to the current N3E process, N3P reduces the number of EUV layers and double-patterning methods, which sacrifices some transistor density but significantly improves yield rates and reduces costs.

Furthermore, TSMC plans to launch its wafer-sharing service, CyberShuttle, in April 2025.