Sarcina Unveils AI Chiplet Platform for 100×100mm Silicon

According to reports, Sarcina Technology has announced the launch of its innovative AI Chiplet platform, designed to deliver advanced AI packaging solutions tailored to specific requirements. This cutting-edge platform enables the creation of silicon systems as large as 100 x 100 mm within a single package.

The platform leverages ASE's FOCoS-CL (Fan-Out Chip-on-Substrate-Chip Last) packaging technology, incorporating an interposer layer that facilitates efficient chip-to-chip interconnects using the UCIe-A standard. This approach provides a cost-effective and customizable solution for next-generation AI computing.

Sarcina is dedicated to developing high-performance, scalable, and power-efficient semiconductor packaging solutions, pushing the boundaries of AI computing system design. As AI workloads continue to evolve, there is an increasing demand for packaging solutions that can accommodate higher computational requirements. The company's advanced interposer packaging technology integrates high-bandwidth memory with efficient interconnects, optimizing AI performance whether the priority is cost, power efficiency, or computing capabilities.

The Sarcina team has successfully developed an interposer that supports data interfaces of up to 64 bits per module, achieving data rates of up to 32 GT/s—meeting the highest UCIe-A performance standards as defined in UCIe 2.0. To further enhance data throughput, multiple modules can be arranged in parallel along the chip's edge. Additionally, LPDDR5X/6 memory and HBM options are available to meet diverse AI application needs.

With extensive expertise in designing high-power, high-performance semiconductor packaging, Sarcina enables AI technology innovators to focus on algorithm development for generative AI and edge AI training without the complexity of post-silicon design and manufacturing. By simply developing their own silicon and leveraging Sarcina's packaging expertise, AI developers can streamline workflows, reduce costs, and maintain high performance. Sarcina's die-to-die interposer solution allows AI processors to form large silicon areas with optimal wafer yields, supporting advanced computing requirements. This large-scale packaging design facilitates higher memory integration, a critical factor for generative AI applications that require rapid parallel data processing.

Key Features of the New Sarcina AI Platform:

· Cost-Optimized Chip Design – A viable alternative to expensive SoC solutions.

· High-Speed Chip-to-Chip Interconnect – Supports UCIe-A standards with up to 64-bit data interfaces per module and 32 GT/s per channel, enabling multi-module configurations, interconnect redundancy, and advanced sideband signaling.

· FOCoS-CL Advanced Packaging Technology – A cost-effective alternative to expensive 2.5D TSV silicon interposers and other high-cost packaging methods such as silicon bridge chips with fan-out RDL interconnects.

· LPDDR5X/6 and HBM Memory Options – Delivers superior bandwidth and efficiency to support various AI workloads. LPDDR6 memory utilizes HBM-like 3D stacking technology, achieving approximately 10 GT/s data rates.

· Scalable Packaging Sizes – Accommodates up to 100 mm x 100 mm to enable flexible AI deployment.

· Power Configurations – Air-cooled solutions operate under 500W, while liquid-cooled configurations can reach up to 1000W for high-performance applications.

· Memory Integration – Supports up to 20 LPDDR5X/6 memory chips or up to 8 HBM3E chips, ensuring high-speed data processing for AI workloads.

Sarcina states that the introduction of its AI Chiplet platform will redefine AI computing capabilities across industries such as autonomous systems, data centers, and scientific computing.