AMD EPYC Processor Taped Out with TSMC 2nm Technology

On Monday, April 14, AMD officially announced the successful tape-out of its sixth-generation EPYC processor, codenamed "Venice." The new chip is expected to launch in 2026 and marks a major milestone in high-performance computing (HPC) development.

"Venice" is the industry's first HPC CPU design to be taped out using TSMC's advanced 2nm (N2) process technology, highlighting both AMD's aggressive product roadmap and TSMC's readiness for next-generation semiconductor manufacturing.

AMD Chair and CEO Dr. Lisa Su emphasized the longstanding strategic collaboration between the two companies, stating that AMD is the first HPC customer for both TSMC's 2nm process and its cutting-edge Fab 21 in Arizona. This achievement underscores the commitment of AMD and TSMC to driving innovation and delivering advanced technologies that power the future of computing.

TSMC Chairman and CEO Dr. C.C. Wei commented that the partnership with AMD has led to significant technology advancements, enabling improved performance, power efficiency, and yield for next-generation silicon wafers.

TSMC's N2 node is its first to leverage gate-all-around (GAA) nanosheet transistors. Compared to the previous N3 (3nm-class) process, the N2 technology is expected to reduce power consumption by 24% to 35% or boost performance by 15% at constant power. Transistor density will also increase by approximately 1.15 times, thanks to the combination of innovative transistor architecture and the optimized N2 NanoFlex design framework.

In addition, AMD has successfully validated silicon for its fifth-generation EPYC processors manufactured at TSMC's Fab 21 facility near Phoenix, Arizona. This milestone enables part of AMD's current EPYC CPU production to be localized in the United States, supporting global manufacturing diversification.