TSMC to Accelerate Arizona Fab Production, Add FOPLP Tech

According to reports, TSMC is significantly accelerating its plans in the United States, with its second semiconductor fabrication plant in Arizona now set to begin production one year ahead of schedule. In a strategic move to meet growing demand for U.S.-manufactured chips, TSMC will also introduce its latest Fan-Out Panel-Level Packaging (FOPLP) technology domestically, enhancing flexibility and resilience in the supply chain.

According to industry sources, this change comes in response to strong demand from major clients such as AMD and Apple. Originally scheduled for equipment installation (P2A phase) in Q4 2026, TSMC has notified partners that machinery will now be moved in and installed as early as September 2025 — a full year ahead of the initial plan.

This means the first phase of the Arizona facility's 3nm process is now expected to enter volume production by the end of 2027. The second phase (P2B), featuring 2nm technology, is targeted for 2028. While this still trails Taiwan's mass production timeline by over two years, it marks a substantial step in expanding advanced node production capacity in the U.S.

A key challenge has been the lack of local back-end packaging and testing capacity. TSMC previously partnered with Amkor for its U.S. packaging operations. However, with a recently announced $100 billion investment plan in the U.S., TSMC has committed to building two state-of-the-art packaging facilities — which will include FOPLP capabilities.

Recent reports indicate that TSMC is finalizing the specifications for its next-generation panel-level packaging technology. The first generation is expected to utilize 300mm x 300mm substrates — smaller than the earlier trial format of 510mm x 515mm. A pilot production line is currently under construction in Taoyuan, Taiwan, with limited output anticipated as early as 2027.

Unlike traditional circular wafers, panel-level packaging offers a larger usable area, which can improve throughput. However, TSMC is initially opting for smaller substrates to maintain tight quality control during early-stage adoption. Initially, TSMC considered collaboration with panel manufacturers like Innolux due to their experience with rectangular substrates. Ultimately, it decided to pursue in-house development after determining that the display industry's precision and technological capabilities were not yet sufficient for cutting-edge packaging requirements.

Panel-level advanced packaging involves placing individual chiplets onto a glass substrate after wafer dicing — a shift from methods like Wafer-on-Wafer (WoW), CoWoS, or SoIC 3D stacking. The glass-based approach offers better thermal performance, though at the cost of lower production efficiency. Industry experts expect this packaging method to be especially appealing for high-performance AI applications in the future.