TSMC N3P in Production, N3X Coming in H2 2024

On April 23, TSMC officially announced that its enhanced N3P (3rd-generation 3nm) process node will enter volume production as scheduled in Q4 2024. Additionally, its next-generation N3X process is expected to enter production in the second half of this year.

The N3P node is an optical shrink of the current N3E process. It retains full design rule and IP compatibility while delivering improved performance and power efficiency. According to TSMC, N3P offers up to 5% higher performance at the same leakage or 5–10% lower power consumption at the same frequency. For designs incorporating mixed logic, SRAM, and analog circuits, the transistor density can increase by approximately 4%.

These improvements in N3P stem from optical process refinements, enabling better scalability across a wide range of chip architectures, especially those requiring high SRAM density. N3P also continues to support IP for both 3nm-class client devices and data center applications.

TSMC confirmed that N3P is now in volume production, with ongoing product development and deployment underway for key partners.

Looking further ahead, the upcoming N3X process offers up to 5% better performance at the same power or 7% lower power at the same frequency compared to N3P. A major breakthrough with N3X is its support for operating voltages up to 1.2V—pushing the limits of 3nm-class technology. This enables extremely high-frequency applications, such as high-end client CPUs, to achieve maximum operating speeds (Fmax). However, developers are advised to manage leakage power carefully, as it could increase by up to 250% at these voltages.

Kevin Zhang, TSMC's Senior Vice President of Business Development and Global Sales and Deputy COO, emphasized that N3P began production at the end of 2024. He reiterated TSMC's commitment to continuous enhancement of each new node, helping customers maximize the benefits of process scaling. “We recognize the significant investment in IP development when transitioning to new nodes, and we want to ensure every process generation delivers long-term value,” Zhang said.

TSMC's strategy includes offering multiple iterations within each process family—such as N5, N5P, N4, N4P, and N4C—to extend equipment lifespan and enable extensive IP reuse. While the industry looks ahead to 2nm technologies, many next-generation client processors—such as those in upcoming iPhone, iPad, and Mac devices—are expected to continue leveraging the N3 process family.