TSMC to Start 2nm Chip Mass Production in H2 2024 with GAA Tech

According to reports, TSMC revealed plans to begin mass production of its cutting-edge N2 (2nm-class) semiconductor process in the second half of 2024. This marks the company's first manufacturing node based on gate-all-around (GAA) nanosheet transistor architecture, a major leap forward in semiconductor innovation.

The N2 process is expected to power a new wave of high-performance chips debuting in 2025. These include AMD's next-generation EPYC "Venice" CPUs for data center applications, as well as client-focused system-on-chips (SoCs) from companies like Apple, targeting smartphones, tablets, and PCs.

Built with GAAFET (Gate-All-Around Field-Effect Transistor) technology, the N2 node promises enhanced performance, increased transistor density, and substantial power efficiency improvements. Compared to the N3E node, N2 delivers a 10–15% boost in performance, a 25–30% reduction in power consumption, and a 15% increase in transistor density—qualifying it as a full-node advancement.

TSMC confirmed that the N2 process is approaching maturity, with transistor performance nearing design targets and average yields of 256Mb SRAM modules exceeding 90%. This milestone indicates a high level of manufacturing readiness as the process transitions into volume production.

As TSMC's first node using GAA nanosheet transistors, the N2 architecture features multiple horizontally stacked nanosheets fully surrounded by the gate. This configuration enhances electrostatic control over the channel, minimizes leakage, and enables more compact transistor dimensions—resulting in significantly higher integration density without compromising power or performance.

In addition to the N2 node, TSMC plans to ramp up production of its advanced A16 and N2P process technologies in 2025, continuing its push toward next-generation semiconductor scalability and performance.