TSMC Roadmap Revealed: 1.6nm in 2026, 1.4nm Accelerates Ahead

TSMC recently introduced its most advanced semiconductor manufacturing technology, the A14 (1.4nm class), during a North America Technology Symposium. The new process directly parallels Intel's upcoming 14A node, with both targeting the 1.4nm class. TSMC has stated that the A14 process will deliver significant improvements in performance, power efficiency, and transistor density over its current N2 (2nm class) technology.

According to TSMC, development of the A14 is progressing ahead of schedule, with early yield targets already achieved. Mass production is expected in 2028, positioning it just ahead of Intel's 14A, which is set to enter risk production in 2027 with potential volume output in 2028.

In an in-depth interview with Tom's Hardware, Dr. Kevin Zhang, Senior Vice President of Business Development at TSMC, shared insight into the company's three-pronged strategic roadmap. The plan is to offer multiple advanced process technologies tailored to distinct market needs, reinforcing TSMC's vision of being “Everyone's Foundry.” This roadmap focuses on three key areas: maximizing transistor density, enhancing power delivery, and enabling advanced multi-chiplet system integration.

To achieve maximum transistor density and performance efficiency, TSMC is optimizing processes for mobile and PC applications with nodes such as N3P, N2, N2P, and A14. These nodes prioritize performance-per-watt while avoiding the complexity and cost of backside power delivery, striking a balance between die area and battery life for mobile and consumer SoCs.

For high-performance computing in data centers—especially processors with power requirements above 1kW—TSMC will introduce the A16 node with backside power delivery (BSPDN) by the end of 2026, followed by the A14 with integrated Super Power Rail (SPR) technology in 2029. These enhancements are aimed at maximizing energy efficiency while controlling costs.

To meet the growing demand for high-performance packaging in data center AI infrastructure, TSMC is expanding its advanced packaging portfolio. The offering includes silicon photonics and embedded power components, enabling high-bandwidth, energy-efficient multi-chiplet system solutions.

Addressing the ongoing debate about the end of Moore's Law, Dr. Zhang noted that the trend from 5nm to A14 has remained consistent. Each generation sees about 30% power efficiency improvement, 15% performance gain, and a 20% increase in transistor density. He emphasized TSMC's confidence in continuing this trajectory, particularly with the major leap from N2 to A16 and the expected maturity of A14 by 2028.

The A14 node represents the next-generation milestone in TSMC's process technology roadmap. The company claims it will significantly outperform today's most advanced 3nm technologies and even the upcoming 2nm nodes slated for later this year. Based on internal data, A14 can deliver up to 15% faster speeds at the same power or reduce power consumption by up to 30% at the same performance compared to N2.

Looking further ahead, TSMC is planning multiple derivatives of the A14 family, including A14P (a high-performance version with backside power delivery), A14X (performance-optimized), and A14C (cost-optimized). In parallel, the A16 node (1.6nm class) is also on track for introduction by the end of 2026.