TSMC Plans 10% Increase in Wafer Foundry Prices
TSMC is reportedly planning to increase its wafer foundry service prices by approximately 10%, a move that has drawn significant attention across the global semiconductor ecosystem. NVIDIA CEO Jensen Huang publicly expressed support for TSMC's pricing, stating that while the cost of advanced process technologies is high, it is “absolutely worth it.”
Industry analysts interpret Huang's remarks as an endorsement of TSMC's value proposition, further highlighting the strong strategic alignment between the two companies. Huang emphasized the complexity and substantial costs associated with building semiconductor fabs and developing sub-2nm process nodes. He also noted that TSMC maintains a consistent and fair pricing structure for all of its clients.
Following a recent meeting and dinner with TSMC Chairman C. C. Wei and his executive team, Huang openly praised the foundry's pricing and technological leadership. Sources familiar with the matter indicated that TSMC's pricing strategy adjustments are driven by multiple factors—including rising construction costs for U.S.-based fabs, global inflationary pressures, foreign exchange volatility, and increasing investments in advanced manufacturing technologies.
Specifically, the cost structure for TSMC's U.S. fabs may prompt up to a 30% increase in pricing for 4nm process nodes, reflecting the higher production expenses tied to "Made in America" initiatives.
During a recent earnings call, Chairman C. C. Wei projected that revenue from AI processors—including CPUs, AI accelerators, and GPUs (excluding networking, edge computing, and endpoint AI)—is expected to double in 2024, with a compound annual growth rate (CAGR) of nearly 45% from 2024 to 2029. With this robust demand trajectory, C. C. Wei stressed the necessity of price adjustments to support massive capital investments and sustain healthy gross margins.
According to industry sources, NVIDIA is already among the initial clients for TSMC's 2nm process and plans to adopt the technology for its next-generation AI chips. As semiconductor nodes shrink further, the complexity and risk of manufacturing increase—making higher wafer pricing an industry-wide inevitability.
Data from electronic design automation (EDA) providers reveal a sharp decline in first-pass silicon success rates. While tape-out success rates hovered around 30% in previous years, they dropped to 24% between 2023 and 2024 and are expected to fall further to 14% by 2025. This trend is largely attributed to the growing customization of chip designs, extended verification cycles, and heightened R&D risks.
As process technology becomes more demanding, IC developers report increasingly close collaboration with foundry partners. Transitioning between foundries requires significant time, manpower, and resources. In an environment where access to cutting-edge nodes is critical for maintaining AI competitiveness, companies are choosing to strengthen long-term partnerships with trusted manufacturers.
IC makers also note that TSMC maintains a volume-based pricing model, where larger orders translate to cost efficiencies. For major customers like NVIDIA, the pressure of higher pricing is mitigated by the benefits of scale, technological leadership, and guaranteed delivery timelines—key advantages in today's AI-driven semiconductor race.
