Samsung Breakthrough in 10nm DRAM for HBM4
Recently, Samsung Electronics announced a significant technological breakthrough in its semiconductor division, successfully surpassing the yield threshold for its sixth-generation (1c) DRAM process at the 10nm-class node. With yields exceeding 50%, Samsung plans to begin mass production of HBM4 — the latest high-bandwidth memory (HBM) — in the second half of the year. This achievement marks a pivotal advancement in Samsung's pursuit of leadership in premium memory solutions.
The 1c DRAM process, approximately 11-12nm, offers higher density, lower power consumption, and thinner die thickness compared to mainstream 1a (14nm) and 1b (12-13nm) DRAM technologies. These characteristics enable more memory layers to be stacked within HBM4 packages, significantly boosting capacity and bandwidth density — essential attributes for AI and high-performance computing (HPC) applications.
Currently, the HBM market is dominated by SK hynix and Micron. SK hynix leads with shipments of HBM4 samples based on 1b DRAM and commands a strong presence in the HBM3E segment with 8-layer and 12-layer configurations. Micron follows closely behind. Although Samsung has supplied HBM3E to AMD, it reportedly failed to pass NVIDIA's qualification tests, limiting its market share in the AI memory sector.
In response, Samsung has been accelerating its 1c DRAM development since last year, led by Hwang Sang-jun, head of the DRAM Development Team. Hwang identified the initial design architecture as the core reason for underperformance in yield and efficiency, stating that "without fundamental corrections at the design stage, meaningful progress is unattainable." This led to a top-down restructuring of Samsung's design and manufacturing collaboration, reflecting the company's resolve to reclaim technological leadership.
As part of its comeback strategy, Samsung plans to supply HBM4 samples in the second half of 2025 and position "customized HBM" as a key strategic focus. HBM4 enables the integration of logic dies with DRAM stacks, leveraging foundry-level process optimizations to tailor solutions for diverse applications. To further enhance performance and system integration, Samsung is adopting its in-house 4nm process for fabricating the logic dies at the base of HBM4 stacks.
Meanwhile, reports indicate that SK hynix is adopting a more conservative approach toward 1c DRAM, prioritizing 1b DRAM for supporting HBM3E and HBM4 production, with plans to introduce 1c DRAM only with the next-generation HBM4E. This provides Samsung with a critical window to gain an early advantage in advanced memory process nodes.
If Samsung continues to improve its 1c DRAM yields, it could narrow the gap with competitors and strengthen its position in the AI and HPC markets, restoring customer confidence. This breakthrough not only validates Samsung's technical capabilities but also signals potential shifts in the competitive landscape of the high-end memory sector. As HBM4 moves into mass production, Samsung is well-positioned to play a more prominent role in the future of AI and high-performance computing.
