Rapidus Starts 2nm Test Production, PDK Due Q1 2026

According to Tom’s Hardware, Japan-based semiconductor foundry startup Rapidus has commenced test production of 2nm process wafers and plans to achieve volume manufacturing of its 2nm technology at the IIM-1 fabrication site by 2027.

Rapidus has begun prototyping test wafers using the 2nm Gate-All-Around (GAA) transistor technology at its IIM-1 plant. The company confirmed that early test wafers have met expected electrical characteristics, indicating that its fabrication equipment is operating correctly and process development is progressing as planned.

Industry experts note that prototyping marks a critical milestone in semiconductor manufacturing, aiming to validate that early test circuits produced with new technology deliver reliable, efficient, and target performance. Rapidus is currently evaluating key electrical parameters of these test circuits, including threshold voltage, drive current, leakage current, subthreshold slope, switching speed, power consumption, and capacitance. While specific test results remain undisclosed, the successful flow of test wafers within the fab itself is highly significant.

Earlier disclosures revealed that construction of the IIM-1 facility began in September 2023, with cleanroom completion in 2024. By June 2025, over 200 advanced tools had been installed, including cutting-edge deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography systems. In December 2024, Rapidus installed an advanced EUV tool and achieved first exposure in April 2025. The plant is now sufficiently mature to run test wafers and measure electrical characteristics of GAA-based circuits to identify potential process issues and fine-tune tool settings or manufacturing steps.

Rapidus highlights that its IIM-1 site will adopt a “single-wafer processing” methodology for all front-end process steps. This semiconductor manufacturing approach treats each wafer independently through processing and inspection, rather than batch processing. While major semiconductor manufacturers employ a hybrid of batch and single-wafer techniques, single-wafer processing is typically reserved for high-precision steps such as lithography, plasma etching, atomic layer deposition, and defect monitoring. Batch processing is more common for oxidation, ion implantation, cleaning, and annealing.

The company plans to apply single-wafer processing comprehensively across all process steps—including oxidation, ion implantation, lithography, deposition, etching, cleaning, and annealing. This enables precise control tailored to each wafer's condition or outcome, allowing engineers to immediately adjust parameters, detect anomalies early, and implement corrections rapidly without waiting for batch completion.

Furthermore, this approach generates higher-resolution data per wafer, enhancing monitoring and optimization via AI-driven algorithms. These algorithms facilitate faster data collection to support continuous process improvement (CPI) aimed at reducing defect density and boosting yield, as well as statistical process control (SPC) to minimize performance variability. The flexibility of single-wafer processing also simplifies adjustments and transitions between low-volume and mass production—an important capability given Rapidus's focus on serving smaller semiconductor customers.

However, single-wafer processing poses challenges, including potentially lower throughput for certain tools compared to batch processing, which can extend cycle times and increase manufacturing costs. It also requires more complex and costly equipment, along with added overhead to coordinate wafer movement through individual process steps. Despite these drawbacks, Rapidus believes the long-term benefits—such as reduced defects, improved yields, and enhanced process control—make single-wafer processing a compelling strategy for 2nm and more advanced node production.

To support early adopters, Rapidus is preparing to release the first version of its Process Design Kit (PDK) in the first quarter of 2026 and is building the necessary infrastructure at the IIM-1 facility to facilitate chip design prototyping.