Rapidus 2nm Logic Density Rivals TSMC, Beats Intel 18A

Industry leaks suggest that Japan's emerging foundry, Rapidus, is making significant strides with its 2nm node, known as 2HP. Early data points to a logic transistor density of 237.31 MTr/mm², nearly identical to TSMC's N2 process at 236.17 MTr/mm², and well ahead of Intel's 18A node at 184.21 MTr/mm² (still an estimate).

The report notes that Rapidus' density figure comes from an HD (high-density) standard cell library with a 138-cell height and G45 track pitch. If comparable to TSMC's N2 library, both nodes appear optimized for maximum logic density, meaning the transistor counts at final release could be very close.

Intel's 18A shows lower density mainly due to two factors: benchmarking against its HD library and the adoption of backside power delivery (BSPDN), which occupies some front-side metal layers. Since Intel prioritizes performance-per-watt efficiency over raw density—and 18A is targeted primarily for internal use—the reduced density is not necessarily a disadvantage in its roadmap.

If the Rapidus 2HP numbers are accurate, it would mark a major leap forward for the company in cutting-edge process technology. According to the current timeline, Rapidus plans to make its 2nm PDK available in early 2026, with volume production expected in 2027.